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公开(公告)号：US20210271305A1
公开(公告)日：2021-09-02
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US12124314B2
公开(公告)日：2024-10-22
申请号：US17207299
申请日：2021-03-19
Applicant: Intel Corporation
Inventor： Alexander Gendler , Adwait Purandare , Ankush Varma , Nazar Haider , Daniela Kaufman , Gilad Bomstein , Shlomo Attias , Amit Gabai , Ariel Szapiro
CPC classification number: G06F1/324 , G06F1/28 , G06F21/554 , G06F21/566 , G06F21/71 , G06F21/81 , G06F2221/034
Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.
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公开(公告)号：US11385704B2
公开(公告)日：2022-07-12
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US20200310511A1
公开(公告)日：2020-10-01
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US20210208659A1
公开(公告)日：2021-07-08
申请号：US17207299
申请日：2021-03-19
Applicant: Intel Corporation
Inventor： Alexander Gendler , Adwait Purandare , Ankush Varma , Nazar Haider , Daniela Kaufman , Gilad Bomstein , Shlomo Attias , Amit Gabai , Ariel Szapiro
Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.
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公开(公告)号：US10936041B2
公开(公告)日：2021-03-02
申请号：US16369793
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/32 , G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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