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公开(公告)号：US10416997B2
公开(公告)日：2019-09-17
申请号：US16164736
申请日：2018-10-18
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark J. Buxton , Zeev Sperber , Koby Gottlieb
IPC: G06F9/30 , G06F7/02 , G06F9/38 , G06F12/0875
Abstract: A method and apparatus for including in processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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公开(公告)号：US20160154647A1
公开(公告)日：2016-06-02
申请号：US15015991
申请日：2016-02-04
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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公开(公告)号：US09043379B2
公开(公告)日：2015-05-26
申请号：US13656636
申请日：2012-10-19
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。 包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。 逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。 或者，分支支持动作可以包括分支到指示的目标代码位置。
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公开(公告)号：US10146536B2
公开(公告)日：2018-12-04
申请号：US15885269
申请日：2018-01-31
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
IPC: G06F9/30 , G06F7/02 , G06F9/38 , G06F12/0875
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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公开(公告)号：US10108416B2
公开(公告)日：2018-10-23
申请号：US15485356
申请日：2017-04-12
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10067761B2
公开(公告)日：2018-09-04
申请号：US15003951
申请日：2016-01-22
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US20180181395A1
公开(公告)日：2018-06-28
申请号：US15885269
申请日：2018-01-31
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
IPC: G06F9/30 , G06F12/0875
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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公开(公告)号：US09898285B2
公开(公告)日：2018-02-20
申请号：US15345221
申请日：2016-11-07
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
IPC: G06F7/50 , G06F9/30 , G06F12/0875
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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公开(公告)号：US20170322804A1
公开(公告)日：2017-11-09
申请号：US15661211
申请日：2017-07-27
Applicant: Intel Corporation
Inventor： Ronen Zohar , Shane Story
Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
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公开(公告)号：US09489198B2
公开(公告)日：2016-11-08
申请号：US15015991
申请日：2016-02-04
Applicant: Intel Corporation
Inventor： Rajiv Kapoor , Ronen Zohar , Mark Buxton , Zeev Sperber , Koby Gottlieb
CPC classification number: G06F9/30021 , G06F7/026 , G06F9/3001 , G06F9/30029 , G06F9/30036 , G06F9/30058 , G06F9/30094 , G06F9/30098 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/3887 , G06F12/0875 , G06F2212/452
Abstract: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
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