公开(公告)号：US11093225B2

公开(公告)日：2021-08-17

申请号：US16454103

申请日：2019-06-27

申请人： Xilinx, Inc.

发明人： Qian Yu ,  Lingzhi Sui ,  Shaoxia Fang ,  Junbin Wang ,  Yi Shan

IPC分类号： G06F8/41 ,  G06F9/30 ,  G06F9/54 ,  G06F9/38 ,  G06N3/08

摘要： A high parallelism computing system and instruction scheduling method thereof are disclosed. The computing system comprises: an instruction reading and distribution module for reading a plurality of types of instructions in a specific order, and distributing the acquired instructions to corresponding function modules according to the types; an internal buffer for buffering data and instructions for performing computation; a plurality of function modules each of which sequentially executes instructions of the present type distributed by the instruction reading and distribution module and reads the data from the internal buffer; and wherein the specific order is obtained by topologically sorting the instructions according to a directed acyclic graph consisting of the types and dependency relationships. By reading the instructions based on the topological sorting the directed acyclic graph constructed according to the types and dependency relationships, the deadlock caused by the instruction dependencies can be avoided by a relatively simple operation.

公开(公告)号：US20240061903A1

公开(公告)日：2024-02-22

申请号：US17892852

申请日：2022-08-22

申请人： Xilinx, Inc.

发明人： Wenzong Yang ,  Wang Xi ,  Yadong Li ,  Junbin Wang ,  Shaoxia Fang

IPC分类号： G06F17/16 ,  G06F7/544 ,  G06F7/552 ,  G06F7/499

CPC分类号： G06F17/16 ,  G06F7/5443 ,  G06F7/552 ,  G06F7/4991

摘要： Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases for the groups. The group-level bias of groupm is dm, and dm is an integer part of a maximum of the power-of-two elements of groupm. A second comparison circuit is configured to determine a greatest one of the respective group-level biases to be a tensor-level bias, dmax.

公开(公告)号：US10902315B2

公开(公告)日：2021-01-26

申请号：US15600806

申请日：2017-05-22

申请人： XILINX, INC.

发明人： Shaoxia Fang ,  Lingzhi Sui ,  Qian Yu ,  Junbin Wang ,  Yi Shan

IPC分类号： G06N3/063 ,  G06F7/544 ,  G06N3/08 ,  G06N3/04

摘要： The present disclosure relates to a processor for implementing artificial neural networks, for example, convolutional neural networks. The processor includes a memory controller group, an on-chip bus and a processor core, wherein the processor core further includes a register map, an instruction module, a data transferring controller, a data writing scheduling unit, a buffer module, a convolution operation unit and a hybrid computation unit. The processor of the present disclosure may be used for implementing various neural networks with increased computation efficiency.