Invention Publication
- Patent Title: LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE
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Application No.: US17878431Application Date: 2022-08-01
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Publication No.: US20230163785A1Publication Date: 2023-05-25
- Inventor: Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR 20210162955 2021.11.24 KR 20220008006 2022.01.19
- Main IPC: H03M13/11
- IPC: H03M13/11

Abstract:
A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
Public/Granted literature
- US11929762B2 Low density parity check decoder and storage device Public/Granted day:2024-03-12
Information query
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