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公开(公告)号：US20240418645A1
公开(公告)日：2024-12-19
申请号：US18408247
申请日：2024-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hojun Lee , Jangwoon Sung , Wookrae Kim , Hyungjin Kim , Seungbeom Park , Junho Shin , Myungjun Lee
Abstract: An example semiconductor measurement apparatus includes a light source, a pattern generator, a stage, an image sensor, and a controller. The light source is configured to output light in a predetermined wavelength band. The pattern generator is configured to generate light including a speckle pattern by scattering the light output from the light source. The stage is disposed on a movement path of the light including the speckle pattern, and a sample reflecting the light including the speckle pattern is seated on the stage. The image sensor is configured to receive light reflected from the sample and generate an original image representing a diffractive pattern of light reflected from the sample. The controller is configured to generate a prediction image for estimating diffractive characteristics of light incident on the image sensor.
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公开(公告)号：US11011228B2
公开(公告)日：2021-05-18
申请号：US16741153
申请日：2020-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsung Cho , Taehui Na , Junho Shin , Makoto Hirano
IPC: G11C13/00
Abstract: A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.
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Patent Agency Ranking
公开(公告)号：US20230163785A1
公开(公告)日：2023-05-25
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1134 , H03M13/112
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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公开(公告)号：US11043268B2
公开(公告)日：2021-06-22
申请号：US16745823
申请日：2020-01-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongmin Baek , Jinyoung Kim , Junho Shin
Abstract: A resistive memory includes a memory cell array, a write/read circuitry and a control circuitry. The memory cell array includes a plurality of resistive memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The write/read circuitry is coupled to the memory cell array through a row decoder and a column decoder, the write/read circuitry performs a write operation to write write data in a target page of the memory cell array, and verifies the write operation by comparing read data read from the target page with the write data. The control circuitry controls at least one of the row decoder, the column decoder and the write/read circuitry to control a resistance which a selected memory cell experiences according to a distance from an access point to the selected memory cell in the memory cell array based on an address.
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公开(公告)号：US20240219315A1
公开(公告)日：2024-07-04
申请号：US18493226
申请日：2023-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jangwoon Sung , Lei Tian , Hao Wang , Jiabei Zhu , Myungjun Lee , Wookrae Kim , Seungbeom Park , Junho Shin , Hojun Lee
IPC: G01N21/95 , G01N21/88 , G01N21/956
CPC classification number: G01N21/9501 , G01N21/8806 , G01N21/956
Abstract: A substrate inspection apparatus includes a light irradiator including an objective lens and a plurality of optical fibers. The objective lens is configured to irradiate light to an illumination area on a semiconductor substrate having a plurality of circuit pattern layers, the plurality of optical fibers are adjacent a periphery of the objective lens and are configured to irradiate the light to a peripheral area adjacent the illumination area. A light generator is configured to generate the light. The light generator is configured to change an irradiation angle of the light to selectively irradiate the light to one or more of the objective lens and the plurality of optical fibers. A light analyzer is configured to obtain images of the circuit pattern layers from the light reflected from the illumination area and the peripheral area. The light analyzer is configured to model each of the circuit pattern layers of the semiconductor substrate to obtain image models and to measure an overlay between the circuit pattern layers through the images and the image models.
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公开(公告)号：US11929762B2
公开(公告)日：2024-03-12
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1137 , H03M13/112 , H03M13/1134
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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7.发明授权公开(公告)号：US11539504B2
公开(公告)日：2022-12-27
申请号：US17336625
申请日：2021-06-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanbyeul Na , Sumin Kim , Hongrak Son , Junho Shin
Abstract: A homomorphic operation accelerator includes a plurality of circuits and a homomorphic operation managing circuit. The plurality of circuits may perform homomorphic operations. The homomorphic operation managing circuit may receive cipher text data, homomorphic encryption information and homomorphic operation information from an external device. The homomorphic operation managing circuit may activate or deactivate each of a plurality of enable signals applied to the plurality of circuits based on the homomorphic encryption information and the homomorphic operation information. The homomorphic operation managing circuit may activate or deactivate each of the plurality of circuits based on the plurality of enable signals. The homomorphic encryption information may be associated with a homomorphic encryption algorithm used to generate the cipher text data. The homomorphic operation information may be associated with the homomorphic operations to be performed on the cipher text data.
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