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公开(公告)号：US11929762B2
公开(公告)日：2024-03-12
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1137 , H03M13/112 , H03M13/1134
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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公开(公告)号：US12255666B2
公开(公告)日：2025-03-18
申请号：US18225313
申请日：2023-07-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Daeyeol Yang , Bohwan Jun , Hongrak Son , Geunyeong Yu , Youngjun Hwang
Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.
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公开(公告)号：US10789127B2
公开(公告)日：2020-09-29
申请号：US16057855
申请日：2018-08-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Geunyeong Yu , Bohwan Jun , Kijun Lee , Junjin Kong , Hong-Rak Son
Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.
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公开(公告)号：US11664826B2
公开(公告)日：2023-05-30
申请号：US17478002
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Heeyoul Kwak , Hongrak Son , Dongmin Shin , Wijik Lee , Bohwan Jun , Youngjun Hwang
CPC classification number: H03M13/2948 , H03M13/096 , H03M13/1108 , H03M13/1575
Abstract: A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.
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公开(公告)号：US20230163785A1
公开(公告)日：2023-05-25
申请号：US17878431
申请日：2022-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kangseok Lee , Geunyeong Yu , Youngjun Hwang , Hongrak Son , Junho Shin , Bohwan Jun , Hyunseung Han
IPC: H03M13/11
CPC classification number: H03M13/1134 , H03M13/112
Abstract: A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.
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Patent Agency Ranking
公开(公告)号：US11562803B2
公开(公告)日：2023-01-24
申请号：US17244195
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Heeyoul Kwak , Bohwan Jun , Hongrak Son , Dongmin Shin , Geunyeong Yu
Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.
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公开(公告)号：US11531871B2
公开(公告)日：2022-12-20
申请号：US16854942
申请日：2020-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehun Jang , Hongrak Son , Changkyu Seol , Geunyeong Yu , Chanho Yoon , Pilsang Yoon
IPC: G06N3/04 , H01L25/18 , G06N3/063 , H01L25/065
Abstract: A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.
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公开(公告)号：US11184030B2
公开(公告)日：2021-11-23
申请号：US16917101
申请日：2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Heeyoul Kwak , Jae Hun Jang , Hong Rak Son , Dong-Min Shin , Geunyeong Yu , Kangseok Lee , Hyunseung Han
Abstract: An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.
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公开(公告)号：US12100465B2
公开(公告)日：2024-09-24
申请号：US17847744
申请日：2022-06-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjun Hwang , Hongrak Son , Geunyeong Yu
CPC classification number: G11C29/52 , G11C7/1039 , G11C7/222 , G11C29/023
Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.
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公开(公告)号：US12080366B2
公开(公告)日：2024-09-03
申请号：US17854638
申请日：2022-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kangseok Lee , Geunyeong Yu , Seonghyeog Choi , Hongrak Son , Youngjun Hwang
CPC classification number: G11C29/52 , G11C29/021 , G11C29/022
Abstract: In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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