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    Processing apparatus and processing method
    2.
    发明授权
    Processing apparatus and processing method 有权

    公开(公告)号：US11531541B2

    公开(公告)日：2022-12-20

    申请号：US16697533

    申请日：2019-11-27

    申请人： Shanghai Cambricon Information Technology Co., Ltd.

    发明人： Tianshi Chen ,  Shengyuan Zhou ,  Zidong Du ,  Qi Guo

    IPC分类号： G06F9/30 ,  G06N3/04 ,  G06N3/08 ,  G06F7/46

    摘要： The present disclosure relates to a processing device including a memory configured to store data to be computed; a computational circuit configured to compute the data to be computed, which includes performing acceleration computations on the data to be computed by using an adder circuit and a multiplier circuit; and a control circuit configured to control the memory and the computational circuit, which includes performing acceleration computations according to the data to be computed. The present disclosure may have high flexibility, good configurability, fast computational speed, low power consumption, and other features.

    METHOD AND APPARATUS FOR OUTPUTTING SIGNALS
    4.
    发明申请
    METHOD AND APPARATUS FOR OUTPUTTING SIGNALS 有权

    公开(公告)号：US20210103311A1

    公开(公告)日：2021-04-08

    申请号：US17064866

    申请日：2020-10-07

    申请人： AGENCY FOR DEFENSE DEVELOPMENT

    发明人： Jong Pyo HAN ,  Seo Hee YANG ,  Jae Ho PARK

    IPC分类号： G06F1/10 ,  G06F7/46

    摘要： This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.

    Method of capturing user control inputs
    5.
    发明授权
    Method of capturing user control inputs 失效
    捕获用户控制输入的方法

    公开(公告)号：US07654459B2

    公开(公告)日：2010-02-02

    申请号：US11274456

    申请日：2005-11-14

    申请人： Timothy J. Orsley ,  Akihiro Machida ,  Tong Xie

    发明人： Timothy J. Orsley ,  Akihiro Machida ,  Tong Xie

    IPC分类号： G06F7/46

    CPC分类号： G06F3/03547 ,  G06F1/1616 ,  G06F1/1632 ,  G06F1/169 ,  G06F3/0317 ,  G06F3/03543 ,  G06F3/038 ,  G06F2203/0338 ,  G06F2203/0384

    摘要： A method of capturing user control inputs includes providing a first navigation member slidably coupled on a housing portion of a portable computer and a stationary second navigation member external to and independent of the portable computer. An input card is provided that includes an optical navigation sensor and is configured with a size and a shape for deployment of the input card in a first releasably fixed arrangement relative to the first navigation member and a second movable arrangement relative to the stationary second navigation member. A first user control input is captured for controlling a function of the portable computer, via communication between the input card and the portable computer, based on relative motion between the optical navigation sensor of the input card and one of respective movable first navigation member and stationary second navigation member.

    摘要翻译： 捕获用户控制输入的方法包括提供可滑动地联接在便携式计算机的壳体部分上的第一导航部件和外部并独立于便携式计算机的固定的第二导航部件。 提供了一种输入卡，其包括光学导航传感器，并且被配置为具有尺寸和形状，用于相对于第一导航构件以第一可释放地固定的布置方式将输入卡展开，并且相对于固定的第二导航构件 。 基于输入卡的光学导航传感器和相应的可移动的第一导航部件之间的相对运动和固定的可移动的第一导航部件之间的相对运动，捕获第一用户控制输入，以通过输入卡和便携式计算机之间的通信来控制便携式计算机的功能 第二导航成员。

    Data processing device having improved interrupt controller to process interrupts of different priority levels
    6.
    发明授权
    Data processing device having improved interrupt controller to process interrupts of different priority levels 失效
    数据处理装置具有改进的中断控制器来处理不同优先级的中断

    公开(公告)号：US5659759A

    公开(公告)日：1997-08-19

    申请号：US742699

    申请日：1996-11-04

    申请人： Yasuo Yamada

    发明人： Yasuo Yamada

    IPC分类号： G06F13/26 ,  G06F7/46

    CPC分类号： G06F13/26

    摘要： In order to delay, as far as possible, the time at which the interrupt request at the newest highest priority level is determined and to shorten the response time for an interrupt request with a high priority level, a microprocessor has control circuit 15, when an interrupt request is received, for inputting an interrupt priority level value obtained from a group of interrupt request signals IPL0# to IPL2 # simultaneously with the input of an interrupt vector for an interrupt request from a plurality of data buses D0 to D15, setting this interrupt level value in a mask register 13 as the mask level when the interrupt process is executed; and controlling a mask circuit 11 for masking an interrupt request of an interrupt priority level the same as or lower than an interrupt priority request level received during the execution of the interrupt process.

    摘要翻译： 为了尽可能延迟确定最新最高优先级的中断请求的时间并缩短具有高优先级的中断请求的响应时间，微处理器具有控制电路15，当一个 接收到中断请求，用于从多个数据总线D0至D15的中断请求的中断向量的输入同时输入从一组中断请求信号IPL0＃获得的中断优先级值到IPL2＃，设置该中断 屏蔽寄存器13中的电平值作为执行中断处理时的掩码级; 以及控制掩码电路11，用于掩蔽中断优先级的中断请求，该中断请求与执行中断处理期间接收到的中断优先级请求级别相同或者更低。