公开(公告)号：US11501158B2

公开(公告)日：2022-11-15

申请号：US16171284

申请日：2018-10-25

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Daofu Liu ,  Xiao Zhang ,  Shaoli Liu ,  Tianshi Chen ,  Yunji Chen

IPC分类号： G06N3/08 ,  G06F9/30 ,  G06N3/04

摘要： Aspects for vector operations in neural network are described herein. The aspects may include a controller unit configured to receive an instruction to generate a random vector that includes one or more elements. The instruction may include a predetermined distribution, a count of the elements, and an address of the random vector. The aspects may further include a computation module configured to generate the one or more elements, wherein the one or more elements are subject to the predetermined distribution.

公开(公告)号：US11531540B2

公开(公告)日：2022-12-20

申请号：US16476262

申请日：2018-04-17

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Tianshi Chen ,  Jie Wei ,  Tian Zhi ,  Zai Wang ,  Shaoli Liu ,  Yuzhe Luo ,  Qi Guo ,  Wei Li ,  Shengyuan Zhou ,  Zidong Du

IPC分类号： G06F7/46 ,  G06N3/04 ,  G06N3/08 ,  G06F9/30

摘要： A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.

公开(公告)号：US11983534B2

公开(公告)日：2024-05-14

申请号：US17929730

申请日：2022-09-05

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Tianshi Chen ,  Shaoli Liu ,  Zai Wang ,  Shuai Hu

IPC分类号： G06F9/30 ,  G06N3/045 ,  G06N3/063

CPC分类号： G06F9/30079 ,  G06F9/3001 ,  G06F9/30025 ,  G06N3/045 ,  G06N3/063

摘要： The present disclosure provides a computing method that is applied to a computing device. The computing device includes: a memory, a register unit, and a matrix computing unit. The method includes the following steps: controlling, by the computing device, the matrix computing unit to obtain a first operation instruction, where the first operation instruction includes a matrix reading instruction for a matrix required for executing the instruction; controlling, by the computing device, an operating unit to send a reading command to the memory according to the matrix reading instruction; and controlling, by the computing device, the operating unit to read a matrix corresponding to the matrix reading instruction in a batch reading manner, and executing the first operation instruction on the matrix. The technical solutions in the present disclosure have the advantages of fast computing speed and high efficiency.