公开(公告)号：US11531540B2

公开(公告)日：2022-12-20

申请号：US16476262

申请日：2018-04-17

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Tianshi Chen ,  Jie Wei ,  Tian Zhi ,  Zai Wang ,  Shaoli Liu ,  Yuzhe Luo ,  Qi Guo ,  Wei Li ,  Shengyuan Zhou ,  Zidong Du

IPC分类号： G06F7/46 ,  G06N3/04 ,  G06N3/08 ,  G06F9/30

摘要： A processing device with dynamically configurable operation bit width, characterized by comprising: a memory for storing data, the data comprising data to be operated, intermediate operation result, final operation result, and data to be buffered in a neural network; a data width adjustment circuit for adjusting the width of the data to be operated, the intermediate operation result, the final operation result, and/or the data to be buffered; an operation circuit for operating the data to be operated, including performing operation on data to be operated of different bit widths by using an adder circuit and a multiplier; and a control circuit for controlling the memory, the data width adjustment circuit and the operation circuit. The device of the present disclosure can have the advantages of strong flexibility, high configurability, fast operation speed, low power consumption or the like.

公开(公告)号：US11507350B2

公开(公告)日：2022-11-22

申请号：US16697603

申请日：2019-11-27

申请人： Cambricon (Xi'an) Semiconductor Co., Ltd.

发明人： Tianshi Chen ,  Shengyuan Zhou ,  Zidong Du ,  Qi Guo

IPC分类号： G06F7/544 ,  G06N3/04 ,  G06N3/08

摘要： The present disclosure relates to a fused vector multiplier for computing an inner product between vectors, where vectors to be computed are a multiplier number vector {right arrow over (A)}{AN . . . A2A1A0} and a multiplicand number {right arrow over (B)} {BN . . . B2B1B0}, {right arrow over (A)} and {right arrow over (B)} have the same dimension which is N+1. The multiplier includes: N+1 multiplication sub-units configured to perform multiplication on each dimension of a vector respectively, and take lower n bits of the multiplier number vector for multiplication each time, where the n bits are removed from the binary number of each dimension of the multiplier number vector after the n bits are taken, and n is larger than 1 and less than N+1; an adder tree configured to perform addition on results of N+1 multiplication sub-units obtained from a same operation each time; and a result register configured to hold a result of every addition performed by the adder tree and send the result to the adder tree for next computation.