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公开(公告)号：US12124945B2
公开(公告)日：2024-10-22
申请号：US17310203
申请日：2019-01-28
发明人： Hangbing Lv , Xiaoxin Xu , Qing Luo , Ming Liu
CPC分类号： G06N3/065 , G11C11/223 , G11C11/2273 , G11C11/54 , H01L29/516 , H01L29/78391
摘要： Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.
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公开(公告)号：US12002500B2
公开(公告)日：2024-06-04
申请号：US17426053
申请日：2019-01-28
发明人： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
CPC分类号： G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C16/14 , G11C16/3404
摘要： A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.
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公开(公告)号：US11205750B2
公开(公告)日：2021-12-21
申请号：US16786346
申请日：2020-02-10
发明人： Qing Luo , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu
摘要： The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
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公开(公告)号：US10665780B2
公开(公告)日：2020-05-26
申请号：US16085400
申请日：2016-03-18
发明人： Ming Liu , Qing Luo , Xiaoxin Xu , Hangbing Lv , Shibing Long , Qi Liu
摘要： A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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公开(公告)号：US20220093150A1
公开(公告)日：2022-03-24
申请号：US17424998
申请日：2019-01-28
发明人： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
IPC分类号： G11C11/22 , H01L27/1159 , H01L27/11597 , H01L29/51 , H01L29/78 , G06N3/063
摘要： The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
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公开(公告)号：US20200176674A1
公开(公告)日：2020-06-04
申请号：US16786346
申请日：2020-02-10
发明人： Qing Luo , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu
IPC分类号： H01L45/00
摘要： The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.
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公开(公告)号：US20230368838A1
公开(公告)日：2023-11-16
申请号：US18247213
申请日：2021-01-25
发明人： Xiaoxin Xu , Jie Yu , Danian Dong , Zhaoan Yu , Hangbing Lv
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C13/0023 , G11C2013/0066
摘要： The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.
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公开(公告)号：US11776607B2
公开(公告)日：2023-10-03
申请号：US17424998
申请日：2019-01-28
发明人： Hangbing Lv , Qing Luo , Xiaoxin Xu , Tiancheng Gong , Ming Liu
CPC分类号： G11C11/223 , G06N3/063 , H01L29/516 , H01L29/78391 , H10B51/20 , H10B51/30
摘要： The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
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公开(公告)号：US20210296579A1
公开(公告)日：2021-09-23
申请号：US17250553
申请日：2018-08-02
发明人： Qi Liu , Hangbing Lv , Ming Liu , Xiaoxin Xu , Cheng Lu , Shengjie Zhao
IPC分类号： H01L45/00
摘要： The present disclosure discloses a resistive random access memory, and the resistive random access memory includes a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer includes a doped HfO2 ferroelectric thin film.
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