公开(公告)号：US20230368838A1

公开(公告)日：2023-11-16

申请号：US18247213

申请日：2021-01-25

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Xiaoxin Xu ,  Jie Yu ,  Danian Dong ,  Zhaoan Yu ,  Hangbing Lv

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0023 ,  G11C2013/0066

Abstract: The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.