Invention Application
- Patent Title: TERMINAL STRUCTURE WITH OPTIMIZED RELIABILITY FOR POWER DEVICE, PREPARATION METHOD THEREFOR AND APPLICATION THEREOF, POWER DEVICE AND PREPARATION METHOD THEREFOR
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Application No.: US18762561Application Date: 2024-07-02
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Publication No.: US20250072095A1Publication Date: 2025-02-27
- Inventor: Yimin WAN , Xiaojun WANG , Qinghai MA , Xiuzhong WANG , Rong CHEN , Haiming BAO
- Applicant: Huahong ZealCore Electronics Technology Co.,Ltd
- Applicant Address: CN Shanghai
- Assignee: Huahong ZealCore Electronics Technology Co.,Ltd
- Current Assignee: Huahong ZealCore Electronics Technology Co.,Ltd
- Current Assignee Address: CN Shanghai
- Priority: CN202311079046.2 20230825
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/285 ; H01L29/40 ; H01L29/417

Abstract:
A terminal structure with optimized reliability for a power semiconductor device, a preparation method therefor, application thereof, a power device and a preparation method therefor are provided. The terminal structure includes a phosphorus-doped silicon oxide layer, a silicon nitride layer, a silicon-rich silicon nitride semi-insulating layer, an undoped silicon dioxide layer, and an organic medium layer. The silicon-rich silicon nitride semi-insulating layer is of an alternating superposition structure of a silicon-rich silicon nitride layer and an ultra-thin silicon nitride barrier layer. The terminal structure effectively prevents external moisture from invading the power device, which improves the robustness of the power device under a moisture condition. The multi-layer silicon-rich silicon nitride is used as a semi-insulating layer, which makes an electric field on a surface of the power device evenly distributed in gradient, prevents the electric field from being gathered at a device terminal.
Information query
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