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公开(公告)号：US11081566B2
公开(公告)日：2021-08-03
申请号：US16354506
申请日：2019-03-15
IPC分类号： H01L29/66 , H01L29/78 , H01L29/417
摘要： Semiconductor devices and methods of forming the same include forming a gate stack in contact with sidewalls of a semiconductor fin and on a bottom spacer over a bottom source/drain region. An encapsulating material is selectively deposited over the gate stack, leaving the bottom spacer exposed. An inter-layer dielectric is formed over the encapsulating material. A via is formed in the inter-layer dielectric to contact the bottom source/drain layer.
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公开(公告)号：US10957583B2
公开(公告)日：2021-03-23
申请号：US16553342
申请日：2019-08-28
发明人： Sean D. Burns , Lawrence A. Clevenger , Matthew E. Colburn , Sivananda K. Kanakasabapathy , Yann A. M. Mignot , Christopher J. Penny , Roger A. Quon , Nicole A. Saulnier
IPC分类号： H01L21/768 , H01L21/02 , H01L21/311 , H01L23/528 , H01L23/522 , H01L23/532 , H01L21/033 , H01L21/027
摘要： An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a β line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a γ line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an α line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a βγβ jog; a βαβ jog; an αβγ jog; a γβα jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.
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公开(公告)号：US10937867B2
公开(公告)日：2021-03-02
申请号：US16515789
申请日：2019-07-18
IPC分类号： H01L29/76 , H01L29/10 , H01L29/06 , H01L29/66 , H01L21/223 , H01L21/324
摘要： A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.
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公开(公告)号：US10510892B2
公开(公告)日：2019-12-17
申请号：US15395637
申请日：2016-12-30
发明人： Huiming Bu , Kangguo Cheng , Dechao Guo , Sivananda K. Kanakasabapathy , Peng Xu
IPC分类号： H01L21/76 , H01L29/78 , H01L29/66 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/06 , H01L21/3065 , H01L21/324 , H01L21/8234 , H01L21/8238 , H01L21/84
摘要： Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
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5.发明申请公开(公告)号：US20190172940A1
公开(公告)日：2019-06-06
申请号：US16267618
申请日：2019-02-05
发明人： Andrew M. Greene , Hong He , Sivananda K. Kanakasabapathy , Gauri Karve , Eric R. Miller , Pietro Montanini
摘要： FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
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公开(公告)号：US10249622B2
公开(公告)日：2019-04-02
申请号：US15602740
申请日：2017-05-23
IPC分类号： H01L29/78 , H01L27/088 , H01L29/161 , H01L29/10 , H01L21/8234 , H01L21/02
摘要： A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.
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公开(公告)号：US10242981B2
公开(公告)日：2019-03-26
申请号：US15445107
申请日：2017-02-28
发明人： Andrew M. Greene , Balasubramanian S. Pranatharthiharan , Sivananda K. Kanakasabapathy , John R. Sporre
IPC分类号： H01L29/06 , H01L27/088 , H01L29/66 , H01L29/78 , H01L29/161 , H01L21/308 , H01L21/027 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12
摘要： A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a substrate, depositing an oxide over the plurality of fins, and applying a cutting mask over a portion of the plurality of fins. The method further includes removing the oxide from the exposed portion of the plurality of fins, depositing a replacement gate stack, and etching portions of the replacement gate stack to remove exposed fins, the exposed fins forming recesses within the semiconductor layer. The method further includes depositing a spacer over the exposed fins and the recesses formed by the removed fins. A portion of the plurality of fins are cut during etching of the replacement gate stack and a portion of the oxide is removed before deposition of the replacement gate stack.
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公开(公告)号：US10242952B2
公开(公告)日：2019-03-26
申请号：US16041878
申请日：2018-07-23
发明人： David J. Conklin , Allen H. Gabor , Sivananda K. Kanakasabapathy , Byeong Y. Kim , Fee Li Lie , Stuart A. Sieg
IPC分类号： H01L21/311 , H01L23/544 , H01L21/308 , G03F7/20 , H01L21/033 , G03F9/00
摘要： Methods of forming a registration mark may include forming a plurality of mandrels over a hard mask over a semiconductor layer, each mandrel including a spacer adjacent thereto. At least one mandrel is selected and a mask is formed over the at least one selected mandrel. The plurality of mandrels are removed leaving the spacers, the mask preventing removal of the at least one selected mandrel. The mask is removed. A first etching patterns the sub-lithographic structures and the registration mark into the hard mask using the spacers as a pattern and the at least one selected mandrel and adjacent spacer for the registration mark. A second etching forms the sub-lithographic structures in the semiconductor layer using the patterned hard mask and to form the registration mark in the semiconductor layer using the at least one selected mandrel and the patterned hard mask.
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公开(公告)号：US10211319B2
公开(公告)日：2019-02-19
申请号：US15633934
申请日：2017-06-27
发明人： Sivananda K. Kanakasabapathy , Gauri Karve , Juntao Li , Fee Li Lie , Stuart A. Sieg , John R. Sporre
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/8234 , H01L21/308 , H01L29/423 , H01L21/84 , H01L27/12
摘要： Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.
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公开(公告)号：US10163721B2
公开(公告)日：2018-12-25
申请号：US15718577
申请日：2017-09-28
发明人： Zhenxing Bi , Donald F. Canaperi , Thamarai S. Devarajan , Sivananda K. Kanakasabapathy , Fee Li Lie , Peng Xu
IPC分类号： H01L21/8234 , H01L29/06 , H01L21/762 , H01L21/311 , H01L29/78 , H01L21/02 , H01L29/66
摘要： A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
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