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    Semiconductor structure and manufacturing method thereof
    1.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11876064B2

    公开(公告)日：2024-01-16

    申请号：US17429305

    申请日：2020-06-15

    申请人： ChangXin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang

    IPC分类号： H01L23/00

    CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/13005 ,  H01L2224/2745 ,  H01L2224/2902

    摘要： A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

    Semiconductor Structure And Manufacturing Method Thereof
    3.
    发明申请
    Semiconductor Structure And Manufacturing Method Thereof 有权

    公开(公告)号：US20220115352A1

    公开(公告)日：2022-04-14

    申请号：US17429592

    申请日：2020-06-15

    申请人： ChangXin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang

    IPC分类号： H01L23/00 ,  H01L21/306

    摘要： The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

    Semiconductor Structure And Manufacturing Method Thereof
    6.
    发明申请
    Semiconductor Structure And Manufacturing Method Thereof 有权

    公开(公告)号：US20220148990A1

    公开(公告)日：2022-05-12

    申请号：US17429305

    申请日：2020-06-15

    申请人： ChangXin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang

    IPC分类号： H01L23/00

    摘要： A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

    Semiconductor structure and manufacturing method thereof
    7.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权

    公开(公告)号：US11855032B2

    公开(公告)日：2023-12-26

    申请号：US17429592

    申请日：2020-06-15

    申请人： ChangXin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang

    IPC分类号： H01L23/00 ,  H01L21/306

    CPC分类号： H01L24/32 ,  H01L21/30604 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/13006 ,  H01L2224/13026 ,  H01L2224/1354 ,  H01L2224/81815

    摘要： The disclosed semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a first solder layer, a barrier layer, and a second solder layer. The metal pad is disposed on the semiconductor substrate; the bump is arranged on the metal pad; the barrier layer is configured on the side of the bump away from the metal pad. The barrier layer includes a first surface and a second surface. The first solder layer is arranged between the bump and the first surface of the barrier layer. The second solder layer is configured on the second surface of the barrier layer. Since the first solder layer and the second solder layer are formed by reflowed and melt solder at a high temperature and can be stretched, the height of the second solder can be adjusted automatically, which reduces the non-wetting problem caused by the package substrate deformation after reflow.

    Wafer stacking method and wafer stacking structure
    8.
    发明授权
    Wafer stacking method and wafer stacking structure 有权

    公开(公告)号：US11545468B2

    公开(公告)日：2023-01-03

    申请号：US17202248

    申请日：2021-03-15

    申请人： Changxin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang ,  Shu-Liang Ning

    IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L21/78 ,  H01L23/48 ,  H01L23/544 ,  H01L25/00

    摘要： A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer, wherein an upper surface of the first wafer includes a first bonding pad configured to connect to a first signal; fabricating a first redistribution layer (RDL) on the first wafer, comprising a first wiring electrically connected to the first bonding pad, and the first wiring includes a first landing pad; bonding a second wafer on the first RDL, wherein the second wafer includes a second bonding pad configured to connect the first signal and located corresponding to the first bonding pad; fabricating a first through silicon via (TSV) with a bottom connected to the first landing pad at a position corresponding to the first landing pad; and fabricating a second RDL on the second wafer to connect the second bonding pad and the first TSV. This wafer stacking method improves the manufacturing yield.

    Wafer stacking method and wafer stacking structure
    9.
    发明授权
    Wafer stacking method and wafer stacking structure 有权

    公开(公告)号：US11348873B2

    公开(公告)日：2022-05-31

    申请号：US17102182

    申请日：2020-11-23

    申请人： Changxin Memory Technologies, Inc.

    发明人： Ling-Yi Chuang ,  Shu-Liang Ning

    IPC分类号： H01L21/50 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

    摘要： A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.