公开(公告)号：US08592257B2

公开(公告)日：2013-11-26

申请号：US13554605

申请日：2012-07-20

Applicant: Mayumi Nakasato ,  Kouichi Saitou

Inventor： Mayumi Nakasato ,  Kouichi Saitou

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2221/68336 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units.

Abstract translation: 一种制造半导体模块的方法包括：将半导体衬底接合到第一绝缘树脂层上; 将半导体衬底切割成多个单独的半导体器件; 通过以双向拉伸方式膨胀第一绝缘树脂层来加宽相邻半导体器件之间的间距; 将多个半导体器件固定到平板上，其中第二绝缘树脂层保持在多个半导体器件和平片之间，并且去除第一绝缘树脂层; 依次层叠多个半导体器件，第三绝缘树脂层和金属板，以形成具有电极的层叠体，用于将器件电极与金属板电连接; 通过选择性地去除所述金属板并形成多个半导体模块来形成布线层; 并将半导体模块分离成单独的单元。

公开(公告)号：US20240321804A1

公开(公告)日：2024-09-26

申请号：US18489886

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dowan Kim ,  Jieun Woo ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package a first package unit comprising a semiconductor chip; and a redistribution structure on the first package unit, wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines, wherein the plurality of wiring lines comprise first subset including a plurality of outermost wiring lines and a second subset, wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit, a respective surface roughness of each of the plurality of outermost wiring lines is different, and the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.

公开(公告)号：US20240096809A1

公开(公告)日：2024-03-21

申请号：US17932624

申请日：2022-09-15

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Onur Ozkan ,  Ali Lehaf ,  Steve Cho ,  Gang Duan ,  Jieping Zhang ,  Rahul N. Manepalli ,  Ravindranath Vithal Mahajan ,  Hamid Azimi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/2201 ,  H01L2224/32225

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.

公开(公告)号：US20120074580A1

公开(公告)日：2012-03-29

申请号：US12890045

申请日：2010-09-24

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/50

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模具，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。

公开(公告)号：US20140117524A1

公开(公告)日：2014-05-01

申请号：US13735603

申请日：2013-01-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo KIM ,  Young Ho SOHN ,  Bum Seok SUH ,  Min Gyu PARK ,  Young Ki LEE

IPC: H01L23/00

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/82 ,  H01L25/162 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2501 ,  H01L2224/25105 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: There are provided a power semiconductor module and a manufacturing method thereof, the power semiconductor module including: a lead frame; a base substrate including a circuit wiring formed on an insulating layer thereof; a plurality of power semiconductor devices disposed to contact the circuit wiring; and a multilayer substrate formed by stacking a plurality of substrates and electrically connecting the power semiconductor devices and the lead frame to one another using a connection line formed therein and having conductivity.

Abstract translation: 提供功率半导体模块及其制造方法，功率半导体模块包括：引线框架; 基底基板，包括形成在其绝缘层上的电路布线; 设置成接触所述电路布线的多个功率半导体器件; 以及通过使用形成在其中并具有导电性的连接线将堆叠多个基板并将功率半导体器件和引线框架彼此电连接而形成的多层基板。

公开(公告)号：US08580616B2

公开(公告)日：2013-11-12

申请号：US13629931

申请日：2012-09-28

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到所述C4焊盘和所述TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入BBUL封装中而不具有PoP焊盘的封装结构。

公开(公告)号：US20130023088A1

公开(公告)日：2013-01-24

申请号：US13629931

申请日：2012-09-28

Applicant: Ravi K. Nalla ,  Mathew Manusharow ,  Pramod Malatkar

Inventor： Ravi K. Nalla ,  Mathew Manusharow ,  Pramod Malatkar

IPC: H01L21/50

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到C4焊盘和TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入在不具有PoP焊盘的BBUL封装内的封装结构。

公开(公告)号：US20120288999A1

公开(公告)日：2012-11-15

申请号：US13554605

申请日：2012-07-20

Applicant: Mayumi NAKASATO ,  Kouichi Saitou

Inventor： Mayumi NAKASATO ,  Kouichi Saitou

IPC: H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2221/68336 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor module includes: bonding a semiconductor substrate onto a first insulating resin layer; dicing the semiconductor substrate into a plurality of individual semiconductor devices; widening the spacings between the adjacent semiconductor devices by expanding the first insulating resin layer in a biaxially stretched manner; fixing the plurality of semiconductor devices to a flat sheet, with a second insulating resin layer held between the plurality of semiconductor devices and the flat sheet, and removing the first insulating resin layer; stacking the plurality of semiconductor devices, a third insulating resin layer, and a metallic plate, in this order, so as to form a laminated body having electrodes by which to electrically connect the device electrodes to the metallic plate; forming a wiring layer by selectively removing the metallic plate and forming a plurality of semiconductor modules; and separating the semiconductor modules into individual units.

Abstract translation: 一种制造半导体模块的方法包括：将半导体衬底接合到第一绝缘树脂层上; 将半导体衬底切割成多个单独的半导体器件; 通过以双向拉伸方式膨胀第一绝缘树脂层来加宽相邻半导体器件之间的间距; 将多个半导体器件固定到平板上，其中第二绝缘树脂层保持在多个半导体器件和平片之间，并且去除第一绝缘树脂层; 依次层叠多个半导体器件，第三绝缘树脂层和金属板，以形成具有电极的层叠体，用于将器件电极与金属板电连接; 通过选择性地去除所述金属板并形成多个半导体模块来形成布线层; 并将半导体模块分离成单独的单元。

公开(公告)号：US11749657B2

公开(公告)日：2023-09-05

申请号：US17476291

申请日：2021-09-15

Applicant: SJ Semiconductor (Jiangyin) Corporation

Inventor： Yenheng Chen ,  Chengchung Lin

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/244 ,  H01L2224/24145 ,  H01L2224/24265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73259

Abstract: The present disclosure provides a fan-out chip packaging structure and a method to fabricate the fan-out chip package. The fan-out chip packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first packaging layer, a stacked chip package, a passive element, a filling layer, a metal bumps, and a second packaging layer. By means of the present disclosure, various chips having different functions can be integrated into one package structure, thereby improving the integration level of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertically stacked package is achieved. In this way, the integration level of the packaging structure can be effectively improved, and the conduction path can be effectively shortened, thereby reducing power consumption, increasing the transmission speed, and increasing the data processing capacity.

公开(公告)号：US08535980B2

公开(公告)日：2013-09-17

申请号：US12977697

申请日：2010-12-23

Applicant: Puay Gek Chua ,  Yonggang Jin

Inventor： Puay Gek Chua ,  Yonggang Jin

IPC: H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  Y10T408/566 ,  H01L2924/014 ,  H01L2924/00

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract translation: 提供了一种用于制造半导体封装的工艺，其包括在重构的晶片中钻孔盲孔，将覆盖在晶片上的干膜抗蚀剂粘附在孔上，以及图案化膜以暴露每个孔周围的空间。 然后通过在胶片的表面上擦拭一定量的糊料，将导电浆料填充到孔和空间中，使得糊料被迫进入空间和孔。 孔周围的空间限定了其厚度受薄膜厚度限制的接触垫，优选为约10μm或更小。 为了防止糊料在孔中捕获气穴，擦拭过程可以在空气中进行大量或全部空气的​​室中进行。 在固化糊料之后，晶片从后面变薄以露出孔中的固化糊料。