公开(公告)号：US20130337310A1

公开(公告)日：2013-12-19

申请号：US14001790

申请日：2012-02-16

Applicant: Tetsuji Omura ,  Mayumi Nakasato ,  Fusanori Watanabe

Inventor： Tetsuji Omura ,  Mayumi Nakasato ,  Fusanori Watanabe

IPC: H01M10/50 ,  H01M2/10

CPC classification number: H01M10/6551 ,  H01M2/1016 ,  H01M2/1077 ,  H01M2/1083 ,  H01M2/14 ,  H01M10/0413 ,  H01M10/613 ,  H01M10/625 ,  H01M10/647 ,  H01M10/653 ,  H01M10/6554 ,  H01M2220/20 ,  Y10T29/4935

Abstract: A cell module 10 comprises: a cell stack 20 comprising multiple cells 30 which are electrically connected to each other; a plate-shaped heat dissipating member 70 arranged such that it extends along a direction in which the multiple cells 30 are arranged, and such that it is thermally connected to the multiple cells 30; and an intervening layer 80 arranged between the cell stack 20 and the heat dissipating member 70, and configured to allow heat to propagate from the cell stack 20 to the heat dissipating member 70, and to suppress a relative displacement between the cell stack 20 and the heat dissipating member 70.

Abstract translation: 电池模块10包括：电池组20，其包括彼此电连接的多个电池30; 布置成使得其沿着多个单元30布置的方向延伸的板状散热构件70，并且使其与多个单元30热连接; 以及布置在电池组20和散热构件70之间的中间层80，并且被配置为允许热量从电池堆20传播到散热构件70，并且抑制电池堆20和电池组20之间的相对位移 散热构件70。

公开(公告)号：US08183090B2

公开(公告)日：2012-05-22

申请号：US12856168

申请日：2010-08-13

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H05K3/10

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部上的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US20110074021A1

公开(公告)日：2011-03-31

申请号：US12895417

申请日：2010-09-30

Applicant: Mayumi NAKASATO ,  Kouichi Saitou ,  Tetsuya Yamamoto

Inventor： Mayumi NAKASATO ,  Kouichi Saitou ,  Tetsuya Yamamoto

IPC: H01L23/48 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/111 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0369 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A device mounting board includes an insulating resin layer, a wiring layer provided on one of main surfaces of the insulating resin layer, and bump electrodes connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A semiconductor module is formed by having the bump electrodes connected to a semiconductor device. A recess is provided in the top face of each bump electrode. The recess communicates with an opening provided on a side surface of the bump electrode.

Abstract translation: 装置安装板包括绝缘树脂层，设置在绝缘树脂层的一个主表面上的布线层以及与布线层电连接并从绝缘树脂层的布线层突出的凸起电极。 通过将凸块电极连接到半导体器件来形成半导体模块。 在每个凸起电极的顶面设置凹部。 凹部与设置在凸块电极的侧面上的开口连通。

公开(公告)号：US20080272502A1

公开(公告)日：2008-11-06

申请号：US12109811

申请日：2008-04-25

Applicant: Mayumi Nakasato ,  Hideki Mizuhara

Inventor： Mayumi Nakasato ,  Hideki Mizuhara

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor module includes: a first process of forming a conductor on one face of an insulating layer; a second process of exposing the conductor from the other face of the insulating layer; a third process of providing a first wiring layer on an exposed area of the conductor and on the other face of the insulating layer; a fourth process of preparing a substrate on which a circuit element is formed, the second wiring being formed on the substrate; and a fifth process of embedding the conductor in the insulating layer by press-bonding the insulating layer and the substrate in a state where the conductor on which the first wiring layer is provided by the third process is disposed counter to the second wiring layer. Wiring is formed without causing damaging to the circuit element.

Abstract translation: 一种制造半导体模块的方法包括：在绝缘层的一个面上形成导体的第一工序; 使导体从绝缘层的另一面露出的第二工序; 在导体的暴露区域和绝缘层的另一面上设置第一布线层的第三工序; 制备其上形成有电路元件的基板的第四工序，在基板上形成第二布线; 以及在通过第三工序设置有第一布线层的导体的状态下，通过将绝缘层和基板压接而将导体埋入绝缘层中的第五工序与第二布线层相反。 形成接线而不会损坏电路元件。

公开(公告)号：US20080105861A1

公开(公告)日：2008-05-08

申请号：US11905748

申请日：2007-10-03

Applicant: Sumio Hosaka ,  Hayato Sone ,  Masaki Yoshimaru ,  Takashi Ono ,  Mayumi Nakasato

Inventor： Sumio Hosaka ,  Hayato Sone ,  Masaki Yoshimaru ,  Takashi Ono ,  Mayumi Nakasato

IPC: H01L47/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148

Abstract: A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layer 26, a second electrode layer 28, and a memory layer 30 provided between the first and second electrode layers 26 and 28 and containing a phase-change material layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature, wherein the memory layer 30 includes a plurality of mutually isolated sub-memory layers 32, 34, 36, and 38 between the first and second electrode layers 26 and 28.

Abstract translation: 可以稳定地记录多值信息并且可以高可靠性再现信息的多值记录相变存储器件包括：第一电极层26，第二电极层28和存储层30， 和第二电极层26和28，并且包含由在室温下在非晶相或结晶相中稳定的相变材料形成的相变材料层，其中存储层30包括多个相互隔离的子 内存层32,34,36和38在第一和第二电极层26和28之间。

公开(公告)号：US20080023841A1

公开(公告)日：2008-01-31

申请号：US11830505

申请日：2007-07-30

Applicant: Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

Inventor： Mayumi Nakasato ,  Hideki Mizuhara ,  Takaya Kusabe ,  Sadamichi Takakusaki

IPC: H01L23/48 ,  H01R12/04 ,  H05K3/02

CPC classification number: H05K3/305 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0262 ,  H05K1/056 ,  H05K1/141 ,  H05K1/183 ,  H05K3/107 ,  H05K3/4614 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09972 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0278 ,  H05K2203/1189 ,  Y02P70/613 ,  Y10T29/49155

Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer. The first and second conductive parts form connecting areas in the insulating layer, thereby connecting the first and second circuit substrates electrically.

Abstract translation: 为了减少设置在芯基板上的电路基板与要安装在其上的电路之间的连接缺陷，从而提高作为多层器件安装基板的可靠性。 装置安装基板包括：由基板，形成在该基板上的绝缘层和形成在该绝缘层上的第一导电层（包括导电部分）构成的第一电路基板; 以及安装在第一电路基板上的第二电路基板，由基底，形成在基底的底部的第二导电层（包括导电部）和形成在基底的顶部的第三导电层 的基地。 这里，第一和第二电路基板通过压力接合，使得第一和第二导电部件层叠并嵌入到绝缘层中。 第一和第二导电部分形成绝缘层中的连接区域，从而电连接第一和第二电路基板。

公开(公告)号：US06887767B2

公开(公告)日：2005-05-03

申请号：US10392878

申请日：2003-03-21

Applicant: Mayumi Nakasato ,  Kazuhiro Sasada ,  Masahiro Oda

Inventor： Mayumi Nakasato ,  Kazuhiro Sasada ,  Masahiro Oda

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76235

Abstract: A method for manufacturing a semiconductor device including forming a buffer film on a semiconductor substrate, forming a element partitioning trench, forming a oxidized film on the surface of the element partitioning trench, and washing the semiconductor substrate with hydrofluoric acid. The washing removes part of the buffer film, and the end of the buffer film is inwardly removed from the top edge of the element partitioning trench by a predetermined distance. The distance and the thickness of the oxidized film are represented by the expression 0≦x≦(d/2 sin θ), where x represents the distance, and θ represents the angle between a plane parallel to the semiconductor substrate and a side surface of the element partitioning trench.

Abstract translation: 一种制造半导体器件的方法，包括在半导体衬底上形成缓冲膜，形成元件分隔沟槽，在元件分隔沟槽的表面上形成氧化膜，并用氢氟酸洗涤半导体衬底。 洗涤物去除部分缓冲膜，缓冲膜的端部从元件分隔槽的顶部边缘向内移除预定距离。 氧化膜的距离和厚度由表达式0 <= x <=（d /2sinθ）表示，其中x表示距离，θ表示平行于半导体衬底的平面与侧面之间的角度 元件分隔沟的表面。

公开(公告)号：US09431686B2

公开(公告)日：2016-08-30

申请号：US14001790

申请日：2012-02-16

Applicant: Tetsuji Omura ,  Mayumi Nakasato ,  Fusanori Watanabe

Inventor： Tetsuji Omura ,  Mayumi Nakasato ,  Fusanori Watanabe

IPC: H01M2/10 ,  H01M10/653 ,  H01M10/04 ,  H01M10/625 ,  H01M10/6551 ,  H01M10/6554 ,  H01M10/613 ,  H01M10/647

CPC classification number: H01M10/6551 ,  H01M2/1016 ,  H01M2/1077 ,  H01M2/1083 ,  H01M2/14 ,  H01M10/0413 ,  H01M10/613 ,  H01M10/625 ,  H01M10/647 ,  H01M10/653 ,  H01M10/6554 ,  H01M2220/20 ,  Y10T29/4935

Abstract: A cell module comprises: a cell stack comprising multiple cells which are electrically connected to each other; a plate-shaped heat dissipating member arranged such that it extends along a direction in which the multiple cells are arranged, and such that it is thermally connected to the multiple cells ; and an intervening layer arranged between the cell stack and the heat dissipating member, and configured to allow heat to propagate from the cell stack to the heat dissipating member, and to suppress a relative displacement between the cell stack and the heat dissipating member.

Abstract translation: 电池模块包括：电池堆，其包括彼此电连接的多个电池; 板状散热构件，其布置成沿着多个单元布置的方向延伸，并且使其与多个单元热连接; 以及布置在电池堆和散热构件之间的中间层，并且被配置为允许热量从电池堆传播到散热构件，并且抑制电池堆与散热构件之间的相对位移。

公开(公告)号：US09024446B2

公开(公告)日：2015-05-05

申请号：US13381299

申请日：2010-06-30

Applicant: Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

Inventor： Ryosuke Usui ,  Yusuke Igarashi ,  Yasunori Inoue ,  Mayumi Nakasato ,  Masayuki Nagamatsu ,  Yasuhiro Kohara

IPC: H05K1/00 ,  H05K3/44 ,  H01L23/373 ,  H05K1/05 ,  H05K1/18 ,  H01L23/00

CPC classification number: H05K3/445 ,  H01L23/3735 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H05K1/05 ,  H05K1/053 ,  H05K1/056 ,  H05K1/185 ,  H05K2201/0195 ,  H05K2201/068 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.

Abstract translation: 传统的印刷电路板具有热辐射特性差的问题，并且用于改善热辐射特性的金属芯印刷电路板具有刚性低和弯曲倾向的问题。 金属的延展性可能受到阻碍，金属受到保护; 通过覆盖由金属作为主要材料构成的金属芯的正面和背面的大部分整个面积与第一陶瓷膜和阻碍上述金属芯的延展性的第二陶瓷膜; 并用绝缘树脂膜覆盖每个陶瓷膜，以覆盖这些陶瓷的脆性。

公开(公告)号：US08378229B2

公开(公告)日：2013-02-19

申请号：US12813978

申请日：2010-06-11

Applicant: Mayumi Nakasato ,  Hideki Mizuhara

Inventor： Mayumi Nakasato ,  Hideki Mizuhara

IPC: H05K1/11

CPC classification number: H01L23/142 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/427 ,  H05K3/445 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/09827 ,  H05K2203/0143 ,  H05K2203/068 ,  Y10T29/49155

Abstract: A circuit board includes a substrate made principally of metal. An opening is provided on the substrate. A first wiring layer is provided on one surface of the substrate via a first insulating layer, and a second wiring layer is provided on the other surface of the substrate via a second insulating layer. A conductor penetrates the substrate via the opening and connects the first wiring layer with the second wiring layer. An end of the opening at one surface side of the substrate has a tapering form on a surface layer thereof, and the first insulating layer has a recess on an upper surface thereof in an upper region of the opening.

Abstract translation: 电路板包括主要由金属制成的基板。 在基板上设置开口。 第一布线层经由第一绝缘层设置在基板的一个表面上，第二布线层经由第二绝缘层设置在基板的另一表面上。 导体经由开口穿透基板，并将第一布线层与第二布线层连接。 在基板的一个表面侧的开口的端部在其表面层上具有渐缩形状，并且第一绝缘层在开口的上部区域中具有在其上表面上的凹部。