公开(公告)号：US12080751B2

公开(公告)日：2024-09-03

申请号：US17742452

申请日：2022-05-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsueh-Han Lu ,  Kun-Ei Chen ,  Chen-Chieh Chiang ,  Ling-Sung Wang ,  Jun-Nan Nian

IPC分类号： H01L49/02 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/822 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L28/24 ,  H01L21/3115 ,  H01L21/76822 ,  H01L21/76825 ,  H01L21/8221 ,  H01L27/0629 ,  H01L27/0688 ,  H01L21/823431

摘要： Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.

公开(公告)号：US11844205B2

公开(公告)日：2023-12-12

申请号：US18171949

申请日：2023-02-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Jen Chen ,  Wen-Hsi Lee ,  Ling-Sung Wang ,  I-Shan Huang ,  Chan-yu Hung

IPC分类号： G06F7/50 ,  H10B10/00 ,  H01L23/528 ,  H01L27/088 ,  G06F30/39 ,  H01L29/78 ,  H01L29/423

CPC分类号： H10B10/12 ,  G06F30/39 ,  H01L23/528 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/42376 ,  H01L29/785

摘要： A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.

公开(公告)号：US10090392B2

公开(公告)日：2018-10-02

申请号：US14158643

申请日：2014-01-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： I-Chih Chen ,  Chih-Mu Huang ,  Ling-Sung Wang ,  Ying-Hao Chen ,  Wen-Chang Kuo ,  Jung-Chi Jeng

IPC分类号： H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L29/45 ,  H01L21/324 ,  H01L23/485 ,  H01L29/165 ,  H01L21/768

摘要： A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.

公开(公告)号：US09893150B2

公开(公告)日：2018-02-13

申请号：US15004365

申请日：2016-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Chieh Chiang ,  Chih-Kang Chao ,  Chih-Mu Huang ,  Ling-Sung Wang ,  Ru-Shang Hsiao

IPC分类号： H01L29/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/1054 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

公开(公告)号：US09837348B2

公开(公告)日：2017-12-05

申请号：US14809478

申请日：2015-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jiun-Jie Huang ,  Ling-Sung Wang

IPC分类号： H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L23/528 ,  H01L21/311 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/7682 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L28/88 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.

公开(公告)号：US09818704B2

公开(公告)日：2017-11-14

申请号：US15339073

申请日：2016-10-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Yao Wang ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L23/562 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76877 ,  H01L22/12 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13147 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.

公开(公告)号：US20170047297A1

公开(公告)日：2017-02-16

申请号：US15339073

申请日：2016-10-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Yao Wang ,  Ying-Han Chiou ,  Ling-Sung Wang

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L23/562 ,  H01L21/76801 ,  H01L21/7681 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76877 ,  H01L22/12 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13147 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

摘要： A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.

摘要翻译： 一种方法包括在晶片的衬底上形成低k电介质层，在低k电介质层上形成第一电介质层，在第一电介质层上形成第二电介质层，在第二电介质层上形成应力调谐电介质层 电介质层，在所述应力调谐电介质层中形成开口以暴露所述第二电介质层的顶表面，以及蚀刻所述应力调谐电介质层和所述第二介电层以形成沟槽。 在单独的蚀刻步骤中进行开口的形成和应力调谐电介质层的蚀刻。 该方法还包括蚀刻第一电介质层以形成连接到沟槽的通孔，并分别填充沟槽和通孔开口以形成金属线和通孔。

公开(公告)号：US09217917B2

公开(公告)日：2015-12-22

申请号：US14192225

申请日：2014-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ru-Shang Hsiao ,  I-I Cheng ,  Jia-Ming Huang ,  Jen-Pan Wang ,  Ling-Sung Wang ,  Chih-Mu Huang

IPC分类号： H01L21/76 ,  G03F1/42 ,  H01L23/544 ,  H01L21/027 ,  G06T7/00

CPC分类号： G03F1/42 ,  G06T7/001 ,  G06T2207/30148 ,  G06T2207/30204 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first material formed on a substrate. The first material includes a first alignment mark. The first alignment mark includes alignment lines in at least three directions. The semiconductor device further includes a second material comprising a second alignment mark. The second alignment mark corresponds to the first alignment mark such that when the second alignment mark is aligned with the first alignment mark, the second material is aligned with the first material.

摘要翻译： 半导体器件包括形成在衬底上的第一材料。 第一材料包括第一对准标记。 第一对准标记包括至少三个方向上的对准线。 半导体器件还包括第二材料，其包括第二对准标记。 第二对准标记对应于第一对准标记，使得当第二对准标记与第一对准标记对准时，第二材料与第一材料对准。

公开(公告)号：US09209270B2

公开(公告)日：2015-12-08

申请号：US14635442

申请日：2015-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/66507 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

公开(公告)号：US09099421B2

公开(公告)日：2015-08-04

申请号：US13665159

申请日：2012-10-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/36 ,  H01L21/02 ,  H01L21/66

CPC分类号： H01L29/36 ,  H01L21/02587 ,  H01L22/12 ,  H01L22/20 ,  H01L29/0684 ,  H01L29/16

摘要： One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

摘要翻译： 本文提供了一种或多种用于控制半导体区域的表面的轮廓的技术或系统。 在一些实施例中，将沉积蚀刻（E / D）比设置为小于1以形成半导体内的区域。 例如，当E / D比小于1时，蚀刻速率小于E / D比的沉积速率，从而“增长”该区域。 在一些实施例中，随后将E / D比设置为大于1。 例如，当E / D比大于1时，蚀刻速率大于E / D比的沉积速率，因此“蚀刻”该区域。 以这种方式，为该区域提供光滑的表面轮廓，至少因为将E / D比设定为大于1，能够使至少一部分生长区域进行回蚀。