公开(公告)号：US11145760B2

公开(公告)日：2021-10-12

申请号：US16582572

申请日：2019-09-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Kuan Jung Chen ,  I-Chih Chen ,  Chih-Mu Huang ,  Ching-Pin Lin ,  Sheng-Lin Hsieh

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66

摘要： A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.

公开(公告)号：US09240503B2

公开(公告)日：2016-01-19

申请号：US14469496

申请日：2014-08-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Che-Min Lin ,  Volume Chien ,  Chih-Kang Chao ,  Chi-Cherng Jeng ,  Pin Chia Su ,  Chih-Mu Huang

IPC分类号： H01L31/0232 ,  H01L31/115 ,  H01L31/10 ,  H01L31/18 ,  H01L27/146

CPC分类号： H01L31/02327 ,  H01L27/14629 ,  H01L31/0232 ,  H01L31/10 ,  H01L31/115 ,  H01L31/18

摘要： A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.

摘要翻译： 光电二极管结构包括设置在光电二极管下方的光电二极管和凹面反射器。 凹面反射器被布置成将来自上方的入射光反射到光电二极管。

公开(公告)号：US20150372045A1

公开(公告)日：2015-12-24

申请号：US14840143

申请日：2015-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-I Cheng ,  Chih-Mu Huang ,  Pin Chia Su ,  Chi-Cherng Jeng ,  Volume Chien ,  Chih-Kang Chao

IPC分类号： H01L27/146 ,  H01L23/58

CPC分类号： H01L27/14645 ,  H01L21/82 ,  H01L23/585 ,  H01L27/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

公开(公告)号：US20240258312A1

公开(公告)日：2024-08-01

申请号：US18602033

申请日：2024-03-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Jung Chen ,  I-Chih Chen ,  Chih-Mu Huang ,  Kai-Di Wu ,  Ming-Feng Lee ,  Ting-Chun Kuan

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin

公开(公告)号：US11955484B2

公开(公告)日：2024-04-09

申请号：US17837046

申请日：2022-06-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Jung Chen ,  I-Chih Chen ,  Chih-Mu Huang ,  Kai-Di Wu ,  Ming-Feng Lee ,  Ting-Chun Kuan

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.

公开(公告)号：US11177306B2

公开(公告)日：2021-11-16

申请号：US16742588

申请日：2020-01-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Volume Chien ,  Yun-Wei Cheng ,  I-I Cheng ,  Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC分类号： H01L31/00 ,  H01L27/146 ,  H01L23/31 ,  H01L23/58 ,  H01L23/00

摘要： Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

公开(公告)号：US09985122B2

公开(公告)日：2018-05-29

申请号：US14949741

申请日：2015-11-23

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Ru-Shang Hsiao ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC分类号： H01L29/51 ,  H01L29/735 ,  H01L29/78 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L29/78 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/66636 ,  H01L29/735 ,  H01L29/7834

摘要： A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (PMID) layer and a composite layer is disclosed. The PMID layer is above the substrate. The composite layer is between the substrate and the PMID layer. The composite layer comprises a first sublayer and a second sublayer. The first sublayer and the second sublayer are stacked. The bandgap of the second sublayer is larger than the bandgap of the first sublayer. The etch rate of an etchant with respect to the first sublayer is lower than the etch rate of the etchant with respect to the substrate and the PMID layer. Other semiconductor structures are also disclosed.

公开(公告)号：US20160343822A1

公开(公告)日：2016-11-24

申请号：US14949741

申请日：2015-11-23

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Ru-Shang Hsiao ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/78 ,  H01L23/291 ,  H01L23/3192 ,  H01L29/66636 ,  H01L29/735 ,  H01L29/7834

摘要： A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (PMID) layer and a composite layer is disclosed. The PMID layer is above the substrate. The composite layer is between the substrate and the PMID layer. The composite layer comprises a first sublayer and a second sublayer. The first sublayer and the second sublayer are stacked. The bandgap of the second sublayer is larger than the bandgap of the first sublayer. The etch rate of an etchant with respect to the first sublayer is lower than the etch rate of the etchant with respect to the substrate and the PMID layer. Other semiconductor structures are also disclosed.

摘要翻译： 公开了一种包括基板，预金属互连电介质（PMID）层和复合层的半导体结构。 PMID层位于衬底之上。 复合层位于基板和PMID层之间。 复合层包括第一子层和第二子层。 堆叠第一子层和第二子层。 第二子层的带隙大于第一子层的带隙。 蚀刻剂相对于第一子层的蚀刻速率低于腐蚀剂相对于衬底和PMID层的蚀刻速率。 还公开了其它半导体结构。

公开(公告)号：US20140210029A1

公开(公告)日：2014-07-31

申请号：US13754612

申请日：2013-01-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： I-I Cheng ,  Chih-Kang Chao ,  Volume Chien ,  Chi-Cherng Jeng ,  Pin Chia Su ,  Chih-Mu Huang

IPC分类号： H01L21/82 ,  H01L27/14

CPC分类号： H01L27/14645 ,  H01L21/82 ,  H01L23/585 ,  H01L27/14 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

摘要： A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

摘要翻译： 模具包括第一多个边缘以及模具中的半导体衬底。 半导体衬底包括第一部分，其包括与第一多个边缘中的相应边缘不对准的第二多个边缘。 半导体衬底还包括从第二多个边缘之一延伸到管芯的第一多个边缘之一的第二部分。 第二部分包括连接到第二多个边缘中的一个边缘的第一端和具有与模具的第一多个边缘中的一个边缘对准的边缘的第二端。

公开(公告)号：US20200152684A1

公开(公告)日：2020-05-14

申请号：US16742588

申请日：2020-01-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Volume Chien ,  Yun-Wei Cheng ,  I-I Cheng ,  Shiu-Ko JangJian ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC分类号： H01L27/146 ,  H01L23/00 ,  H01L23/31 ,  H01L23/58

摘要： Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.