Semiconductor structure
    1.
    发明授权

    公开(公告)号:US11271102B2

    公开(公告)日:2022-03-08

    申请号:US16717528

    申请日:2019-12-17

    摘要: A semiconductor structure includes a substrate, a gate region, a source/drain region, a composite layer, an ILD layer, a first plug and a second plug. The composite layer includes a first sublayer and a third layer including a first material, and a second sublayer including a second material. The second sublayer is between the first sublayer and the third sublayer. The first plug is through the ILD layer and electrically connected to the gate region. The second plug is through the ILD layer and the composite layer and electrically connected to the source/drain region. The second plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer. Widths of the first portion and the third portion are smaller than a width of the second portion. The second portion has a substantially curved sidewall profile.

    Semiconductor structure and manufacturing method thereof

    公开(公告)号:US10651041B2

    公开(公告)日:2020-05-12

    申请号:US16429595

    申请日:2019-06-03

    摘要: A semiconductor structure and a method of forming the same are provided. According to an aspect of the disclosure, a semiconductor structure includes a first layer having a bottom portion and a sidewall connected to the bottom portion, a metal layer disposed above the bottom portion of the first layer, and a second layer disposed above the metal layer and laterally surrounded by the sidewall of the first layer. The metal layer includes a periphery and a middle portion surrounded by the periphery, the middle portion being thicker than the periphery, and a first etch rate of an etchant with respect to the metal layer is uniform throughout the metal layer and is greater than a second etch rate of the etchant with respect to the second layer.

    Metal gate stack having TaAlCN layer

    公开(公告)号:US10483112B2

    公开(公告)日:2019-11-19

    申请号:US16042527

    申请日:2018-07-23

    摘要: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.

    Support Structure for Integrated Circuitry
    4.
    发明申请

    公开(公告)号:US20190326343A1

    公开(公告)日:2019-10-24

    申请号:US16459181

    申请日:2019-07-01

    摘要: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

    Structure of dielectric grid with a metal pillar for semiconductor device
    8.
    发明授权
    Structure of dielectric grid with a metal pillar for semiconductor device 有权
    具有半导体器件金属柱的电介质栅结构

    公开(公告)号:US09130077B2

    公开(公告)日:2015-09-08

    申请号:US13968260

    申请日:2013-08-15

    IPC分类号: H01L31/0232 H01L31/18

    摘要: An image sensor device and a method for manufacturing the image sensor device are provided. An image sensor device includes a substrate, sensor elements disposed at a front surface of the substrate, and a dielectric grid disposed over a back surface of the substrate. The dielectric grid includes a first dielectric layer as a bottom portion, a metal pillar, as a core portion of a upper portion, disposed over the first dielectric layer and a second dielectric layer wrapping around the metal pillar. The image sensor device also includes a stack of layers disposed over the back surface of the substrate. Refractive index of each layers increases from top layer to bottom layer. The image sensor device also includes a color filter and a microlens disposed over the back surface of the substrate.

    摘要翻译: 提供了图像传感器装置和图像传感器装置的制造方法。 图像传感器装置包括基板,设置在基板的前表面的传感器元件和布置在基板的后表面上的电介质栅格。 电介质栅格包括作为底部的第一电介质层,设置在第一电介质层上的作为上部的芯部的金属柱和围绕金属柱缠绕的第二电介质层。 图像传感器装置还包括设置在基板的背面上的层叠层。 每层的折射率从顶层增加到底层。 图像传感器装置还包括滤色器和设置在基板的后表面上的微透镜。

    Protection Layer In CMOS Image Sensor Array Region
    9.
    发明申请
    Protection Layer In CMOS Image Sensor Array Region 有权
    CMOS图像传感器阵列区域中的保护层

    公开(公告)号:US20150189207A1

    公开(公告)日:2015-07-02

    申请号:US14144229

    申请日:2013-12-30

    IPC分类号: H04N5/374

    摘要: A semiconductor image sensor device having a conformal protective layer includes a semiconductor substrate a pixel-array region and a peripheral region. The conformal protective layer is disposed over a plurality of pixels having a photodiode and a plurality of transistors in the pixel-array region. Contacts to the plurality of transistors are surrounded by the conformal protective layer. In some embodiments, the conformal protective layer is the same material as transistor gate spacers in the peripheral region.

    摘要翻译: 具有共形保护层的半导体图像传感器装置包括半导体衬底,像素阵列区域和外围区域。 保形层设置在像素阵列区域中具有光电二极管和多个晶体管的多个像素上。 与多个晶体管的接触被保形层包围。 在一些实施例中,共形保护层与外围区域中的晶体管栅极间隔物相同。

    Method and Structure for Reducing Light Crosstalk in Integrated Circuit Device
    10.
    发明申请
    Method and Structure for Reducing Light Crosstalk in Integrated Circuit Device 有权
    集成电路设备中减轻光串扰的方法与结构

    公开(公告)号:US20150003777A1

    公开(公告)日:2015-01-01

    申请号:US13930717

    申请日:2013-06-28

    IPC分类号: G02B6/12 H01L27/146 G02B6/13

    摘要: The present disclosure provides an integrated circuit device comprising a substrate having a back surface and a sensing region disposed in the substrate and being operable to sense radiation projected towards the back surface of the substrate. The device further includes a waveguide disposed over the back surface of the substrate. The waveguide is aligned with the sensing region such that the waveguide is operable to transmit the radiation towards the aligned sensing region. The waveguide includes a waveguide wall, and an inner region disposed adjacent to the waveguide wall. A diffractive index of the waveguide wall is less than a diffractive index of the inner region.

    摘要翻译: 本公开提供了一种集成电路器件,其包括具有背表面和设置在衬底中的感测区域的衬底,并且可操作以感测朝向衬底的背表面投射的辐射。 该器件还包括布置在衬底的背面上的波导管。 波导与感测区域对准,使得波导可操作以将辐射传送到对准的感测区域。 波导包括波导壁和邻近波导壁设置的内部区域。 波导壁的衍射指数小于内部区域的衍射指数。