公开(公告)号：US20240304603A1

公开(公告)日：2024-09-12

申请号：US18668408

申请日：2024-05-20

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/11 ,  H01L29/739 ,  H10N30/50

CPC分类号： H01L25/071 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H10N30/50 ,  H01L23/5385 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

摘要： A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US20180261561A1

公开(公告)日：2018-09-13

申请号：US15892460

申请日：2018-02-09

申请人： MEDIATEK INC.

发明人： Chun-Liang CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L23/562 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05076 ,  H01L2224/05085 ,  H01L2224/05093 ,  H01L2224/05099 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/301 ,  H01L2924/3512 ,  H01L2224/45099

摘要： A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

公开(公告)号：US20180233491A1

公开(公告)日：2018-08-16

申请号：US15954326

申请日：2018-04-16

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC分类号： H01L25/07 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/11 ,  H01L25/00 ,  H01L29/739 ,  H01L41/083

CPC分类号： H01L25/071 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

摘要： A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US09847294B2

公开(公告)日：2017-12-19

申请号：US15432906

申请日：2017-02-14

申请人： MEDIATEK INC.

发明人： Chun-Liang Chen ,  Tien-Chang Chang ,  Chien-Chih Lin

IPC分类号： H01L23/52 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L27/088

CPC分类号： H01L23/5286 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014

摘要： The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.

公开(公告)号：US20170069574A1

公开(公告)日：2017-03-09

申请号：US15356680

申请日：2016-11-21

申请人： MEDIATEK INC.

发明人： Chun-Liang Chen

IPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/05085 ,  H01L2224/05624 ,  H01L2924/00014

摘要： A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

摘要翻译： 半导体器件可以包括金属焊盘和第一特定金属层布线。 金属焊盘位于半导体器件的第一金属层上，并与第一金属层直接接触。 第一特定金属层布线形成在半导体器件的第二金属层上并在金属焊盘下方。 此外，半导体器件可以包括至少一个通孔插头，用于将第一特定金属层布线连接到第一金属层中的至少一个金属区域，其中上述至少一个通孔插塞直接形成在金属垫下方。

公开(公告)号：US09202794B2

公开(公告)日：2015-12-01

申请号：US13803429

申请日：2013-03-14

申请人： SAMSUNG Electronics Co., Ltd.

发明人： Nam-Gyu Baek ,  Young-Min Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/03 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/08113 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

摘要： A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion- to provide high roughness and firm connection.

摘要翻译： 可用于半导体器件的焊盘结构可以包括绝缘层图案结构，插头和焊盘。 绝缘层图案结构具有插塞孔和至少一个通孔。 插头形成在插头孔中。 衬垫形成在绝缘层图案结构上。 垫与插头电连接，具有下表面和不平的上表面。 下表面包括插入通孔的突出部分。 不平坦的上表面包括凹部和升高部分，以提供高粗糙度和牢固的连接。

公开(公告)号：US09093430B2

公开(公告)日：2015-07-28

申请号：US14059102

申请日：2013-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： I-Chih Chen ,  Ying-Hao Chen ,  Chi-Cherng Jeng ,  Volume Chien ,  Fu-Tsun Tsai ,  Kun-Huei Lin

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： H01L23/5226 ,  G06F17/5077 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16145 ,  H01L2224/29006 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

摘要： A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

摘要翻译： 半导体器件包括包括多个第一层金属焊盘的第一层，形成在第一层顶部上的第二层，第二层包括多个第二层金属焊盘，以及将第一层金属焊盘连接到第二层金属焊盘的通孔 层金属垫。 第一层金属焊盘和第二层金属焊盘之间的表面积重叠低于规定的阈值。

公开(公告)号：US20150090480A1

公开(公告)日：2015-04-02

申请号：US14042662

申请日：2013-09-30

申请人： TU-ANH N. TRAN ,  Chu-Chung Lee

发明人： TU-ANH N. TRAN ,  Chu-Chung Lee

IPC分类号： H05K1/11 ,  H05K3/40 ,  H05K1/09

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85207 ,  H01L2224/8581 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  Y10T29/49124 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01012 ,  H01L2924/01016 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.

摘要翻译： 电子部件封装包括基板和电介质结构。 电介质结构包括具有突出部分和下部分的顶表面。 突出部位于大于下部的第二高度的第一高度。 导电接合焊盘位于电介质结构之上。 球接合电耦合接合焊盘和接合线。 位于球焊接和焊盘之间的金属间化合物由球焊和焊盘的材料形成，并将焊接焊盘电连接到球焊上。 接合焊盘的一部分垂直地位于电介质结构的顶表面的下部的一部分和金属间化合物之间。 接合焊盘的没有部分垂直地位于突出部分的至少一部分和金属间化合物之间。

公开(公告)号：US20140217601A1

公开(公告)日：2014-08-07

申请号：US14165594

申请日：2014-01-28

申请人： MEDIATEK INC.

发明人： Chun-Liang Chen ,  Tien-Chang Chang ,  Chien-Chih Lin

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014

摘要： The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed on a second metal layer of the semiconductor device, and directly under the metal pad.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括：金属焊盘和第一特定金属层布线。 金属焊盘位于半导体器件的第一金属层上。 第一特定金属层布线形成在半导体器件的第二金属层上，并且直接在金属焊盘下方。

公开(公告)号：US08723315B2

公开(公告)日：2014-05-13

申请号：US13470572

申请日：2012-05-14

申请人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

发明人： Jong-Joo Lee ,  Tae-Joo Hwang ,  Cha-Jea Jo

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

摘要： A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

摘要翻译： 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。