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    Pad structure and integrated circuit die using the same
    1.
    发明授权
    Pad structure and integrated circuit die using the same 有权

    公开(公告)号：US10910330B2

    公开(公告)日：2021-02-02

    申请号：US15892460

    申请日：2018-02-09

    Applicant: MEDIATEK INC.

    Inventor： Chun-Liang Chen

    IPC: H01L23/00

    Abstract: A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

    Semiconductor device allowing metal layer routing formed directly under metal pad
    7.
    发明授权
    Semiconductor device allowing metal layer routing formed directly under metal pad 有权
    半导体器件允许直接在金属焊盘下方形成金属层布线

    公开(公告)号：US09536833B2

    公开(公告)日：2017-01-03

    申请号：US15164889

    申请日：2016-05-26

    Applicant: MEDIATEK INC.

    Inventor： Chun-Liang Chen

    IPC: H01L23/52 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522

    CPC classification number: H01L23/5286 ,  H01L23/485 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/05085 ,  H01L2224/05624 ,  H01L2924/00014

    Abstract: A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

    Abstract translation: 半导体器件可以包括金属焊盘和第一特定金属层布线。 金属焊盘位于半导体器件的第一金属层上，并与第一金属层直接接触。 第一特定金属层布线形成在半导体器件的第二金属层上并在金属焊盘下方。 此外，半导体器件可以包括至少一个通孔插头，用于将第一特定金属层布线连接到第一金属层中的至少一个金属区域，其中上述至少一个通孔插塞直接形成在金属垫下方。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160372431A1

    公开(公告)日：2016-12-22

    申请号：US15250888

    申请日：2016-08-29

    Applicant: MEDIATEK INC.

    Inventor： Chun-Liang Chen ,  Tien-Chang Chang ,  Chien-Chih Lin

    IPC: H01L23/00

    CPC classification number: H01L23/5286 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014

    Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

    Abstract translation: 本发明提供一种半导体器件。 半导体器件包括：金属焊盘和第一特定金属层布线和第二特定金属层布线。 金属焊盘位于半导体器件的第一金属层上。 第一特定金属层布线和第二特定金属层布线形成在半导体器件的第二金属层中，其中第一特定金属层布线直接在金属焊盘下方，并且第二特定金属层布线不直接位于 金属垫。

    Storage Device Calibration Methods and Controlling Device Using the Same
    9.
    发明申请
    Storage Device Calibration Methods and Controlling Device Using the Same 有权
    存储设备校准方法及使用其的控制设备

    公开(公告)号：US20160132379A1

    公开(公告)日：2016-05-12

    申请号：US14535335

    申请日：2014-11-07

    Applicant: MEDIATEK INC.

    Inventor： Chun-Liang Chen

    IPC: G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/0772 ,  G01R1/0466 ,  G01R1/0491 ,  G01R31/043 ,  G01R31/265 ,  G01R31/2868 ,  G01R31/2874 ,  G01R31/318511 ,  G06F11/00 ,  G06F11/0787 ,  G06F11/1492 ,  G06F11/22 ,  G11C11/00 ,  G11C29/00 ,  G11C29/023 ,  G11C29/028 ,  G11C29/44 ,  H04L1/00

    Abstract: A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful.

    Abstract translation: 校准方法包括根据多个训练参数组中的每一个将包括校准数据和第一校验和的第一数据发送到存储设备; 分别记录与所述多个训练参数组对应的多个误差指示符和所述存储装置; 根据与多个训练参数组对应的多个误差指示符，将多个训练参数组中的一个识别为预定参数集; 其中每个错误指示符指示是否成功地根据对应的训练参数集发送第一数据。

    APPARATUS AND METHOD FOR CONTROLLING CONTROLLABLE CLOCK SOURCE TO GENERATE CLOCK SIGNAL WITH FREQUENCY TRANSITION
    10.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING CONTROLLABLE CLOCK SOURCE TO GENERATE CLOCK SIGNAL WITH FREQUENCY TRANSITION 审中-公开
    用于控制可控时钟源的方法和方法，用于生成具有频率转换的时钟信号

    公开(公告)号：US20150033062A1

    公开(公告)日：2015-01-29

    申请号：US14325368

    申请日：2014-07-08

    Applicant: MEDIATEK INC.

    Inventor： You-Ming Tsao ,  Chun-Liang Chen ,  Chen-Chia Lee

    IPC: G06F1/08 ,  G06F12/14 ,  H03K5/00

    CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/1689 ,  Y02D10/126

    Abstract: A clock generator includes a controllable clock source and a frequency hopping controller. The controllable clock source generates a clock signal to a clock-driven device. The frequency hopping controller controls the controllable clock source to make the clock signal have at least one frequency transition from one clock frequency to another clock frequency, wherein the controllable clock source stays in a frequency-locked state during a time period of the at least one frequency transition.

    Abstract translation: 时钟发生器包括可控时钟源和跳频控制器。 可控时钟源产生时钟驱动器件的时钟信号。 跳频控制器控制可控时钟源，使得时钟信号具有从一个时钟频率到另一个时钟频率的至少一个频率转换，其中可控时钟源在至少一个时钟频率的时间段期间保持在频率锁定状态 频率转换。

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