公开(公告)号：US09099421B2

公开(公告)日：2015-08-04

申请号：US13665159

申请日：2012-10-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/36 ,  H01L21/02 ,  H01L21/66

CPC分类号： H01L29/36 ,  H01L21/02587 ,  H01L22/12 ,  H01L22/20 ,  H01L29/0684 ,  H01L29/16

摘要： One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

摘要翻译： 本文提供了一种或多种用于控制半导体区域的表面的轮廓的技术或系统。 在一些实施例中，将沉积蚀刻（E / D）比设置为小于1以形成半导体内的区域。 例如，当E / D比小于1时，蚀刻速率小于E / D比的沉积速率，从而“增长”该区域。 在一些实施例中，随后将E / D比设置为大于1。 例如，当E / D比大于1时，蚀刻速率大于E / D比的沉积速率，因此“蚀刻”该区域。 以这种方式，为该区域提供光滑的表面轮廓，至少因为将E / D比设定为大于1，能够使至少一部分生长区域进行回蚀。

公开(公告)号：US09831314B2

公开(公告)日：2017-11-28

申请号：US14816503

申请日：2015-08-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/36 ,  H01L29/06 ,  H01L29/16 ,  H01L21/66 ,  H01L21/02

CPC分类号： H01L29/36 ,  H01L21/02587 ,  H01L22/12 ,  H01L22/20 ,  H01L29/0684 ,  H01L29/16

摘要： One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

公开(公告)号：US09564487B2

公开(公告)日：2017-02-07

申请号：US14180394

申请日：2014-02-14

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Ru-Shang Hsiao ,  Chia-Ming Chang ,  Huang Jiun-Jie ,  Ling-Sung Wang

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC分类号： H01L29/1033 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

摘要： Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a first channel region and a second channel region that are formed according to at least one of a vertical channel configuration or a dual channel configuration. The first channel region operates as a first channel between a source region and a drain region of the semiconductor arrangement. The second channel region operates as a second channel between the source region and the drain region. A gate region, formed between the first channel region and the second channel region, operates to control the first channel and the second channel. Performance of the semiconductor arrangement is improved, such as an increase in current, because two current paths between the source region and the drain region are provided by the two channels.

摘要翻译： 除此之外，本文提供了一种或多种用于形成这种半导体布置的半导体布置和技术。 半导体装置包括根据垂直通道配置或双通道配置中的至少一个形成的第一通道区域和第二通道区域。 第一沟道区域作为半导体装置的源极区域和漏极区域之间的第一沟道工作。 第二沟道区在源区和漏区之间作为第二沟道工作。 形成在第一通道区域和第二通道区域之间的栅极区域操作以控制第一通道和第二通道。 因为源极区域和漏极区域之间的两个电流路径由两个通道提供，所以提高了半导体装置的性能，例如电流的增加。

公开(公告)号：US08940594B2

公开(公告)日：2015-01-27

申请号：US13726270

申请日：2012-12-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L21/8234 ,  H01L21/36 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/06 ,  H01L29/1058 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.

摘要翻译： 其中，本文提供半导体器件或晶体管以及用于形成半导体器件的方法。 半导体器件包括一个或多个V形凹槽，其中生长诸如硅锗的应力单晶半导体材料，以形成半导体器件的源极或漏极中的至少一个。 一个或多个V形凹槽原位蚀刻到基底中。 当半导体器件（例如，第一晶体管）的第一部分和半导体器件的第二部分（例如，第一晶体管）之间的多晶间隔时，半导体器件包括高度与长度之比超过至少1.6的源极或漏极中的至少一个 （例如，第二晶体管）小于约60nm。

公开(公告)号：US09269812B2

公开(公告)日：2016-02-23

申请号：US14600095

申请日：2015-01-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/78 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/06 ,  H01L29/1058 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.

摘要翻译： 其中，本文提供半导体器件或晶体管以及用于形成半导体器件的方法。 半导体器件包括一个或多个V形凹槽，其中生长诸如硅锗的应力单晶半导体材料，以形成半导体器件的源极或漏极中的至少一个。 一个或多个V形凹槽原位蚀刻到基底中。 当半导体器件（例如，第一晶体管）的第一部分和半导体器件的第二部分（例如，第一晶体管）之间的多晶间隔时，半导体器件包括高度与长度之比超过至少1.6的源极或漏极中的至少一个 （例如，第二晶体管）小于约60nm。

公开(公告)号：US20150340447A1

公开(公告)日：2015-11-26

申请号：US14816503

申请日：2015-08-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/36 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/36 ,  H01L21/02587 ,  H01L22/12 ,  H01L22/20 ,  H01L29/0684 ,  H01L29/16

摘要： One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

摘要翻译： 本文提供了一种或多种用于控制半导体区域的表面的轮廓的技术或系统。 在一些实施例中，将沉积蚀刻（E / D）比设置为小于1以形成半导体内的区域。 例如，当E / D比小于1时，蚀刻速率小于E / D比的沉积速率，从而“增长”该区域。 在一些实施例中，随后将E / D比设置为大于1。 例如，当E / D比大于1时，蚀刻速率大于E / D比的沉积速率，因此“蚀刻”该区域。 以这种方式，为该区域提供光滑的表面轮廓，至少因为将E / D比设定为大于1，能够使至少一部分生长区域进行回蚀。

公开(公告)号：US20150236094A1

公开(公告)日：2015-08-20

申请号：US14180394

申请日：2014-02-14

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Ru-Shang Hsiao ,  C.M. Chang ,  Huang Jiun-Jie ,  Ling-Sung Wang

IPC分类号： H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

摘要： Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided herein. A semiconductor arrangement comprises a first channel region and a second channel region that are formed according to at least one of a vertical channel configuration or a dual channel configuration. The first channel region operates as a first channel between a source region and a drain region of the semiconductor arrangement. The second channel region operates as a second channel between the source region and the drain region. A gate region, formed between the first channel region and the second channel region, operates to control the first channel and the second channel. Performance of the semiconductor arrangement is improved, such as an increase in current, because two current paths between the source region and the drain region are provided by the two channels.

摘要翻译： 除此之外，本文提供了一种或多种用于形成这种半导体布置的半导体布置和技术。 半导体装置包括根据垂直通道配置或双通道配置中的至少一个形成的第一通道区域和第二通道区域。 第一沟道区域作为半导体装置的源极区域和漏极区域之间的第一沟道工作。 第二沟道区在源区和漏区之间作为第二沟道工作。 形成在第一通道区域和第二通道区域之间的栅极区域操作以控制第一通道和第二通道。 因为源极区域和漏极区域之间的两个电流路径由两个通道提供，所以提高了半导体装置的性能，例如电流的增加。

公开(公告)号：US20150137182A1

公开(公告)日：2015-05-21

申请号：US14600095

申请日：2015-01-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L27/092 ,  H01L29/161

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/06 ,  H01L29/1058 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.

摘要翻译： 其中，本文提供半导体器件或晶体管以及用于形成半导体器件的方法。 半导体器件包括一个或多个V形凹槽，其中生长诸如硅锗的应力单晶半导体材料，以形成半导体器件的源极或漏极中的至少一个。 一个或多个V形凹槽原位蚀刻到基底中。 当半导体器件（例如，第一晶体管）的第一部分和半导体器件的第二部分（例如，第一晶体管）之间的多晶间隔时，半导体器件包括高度与长度之比超过至少1.6的源极或漏极中的至少一个 （例如，第二晶体管）小于约60nm。

公开(公告)号：US20140175556A1

公开(公告)日：2014-06-26

申请号：US13726270

申请日：2012-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L27/092 ,  H01L21/36

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/06 ,  H01L29/1058 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device. The one or more v-shaped recesses are etched into a substrate in-situ. The semiconductor device comprises at least one of a source or a drain having a height-to-length ratio exceeding at least 1.6 when poly spacing between a first part of the semiconductor device (e.g., first transistor) and a second part of the semiconductor device (e.g., second transistor) is less than about 60 nm.

摘要翻译： 其中，本文提供半导体器件或晶体管以及用于形成半导体器件的方法。 半导体器件包括一个或多个V形凹槽，其中生长诸如硅锗的应力单晶半导体材料，以形成半导体器件的源极或漏极中的至少一个。 一个或多个V形凹槽原位蚀刻到基底中。 当半导体器件（例如，第一晶体管）的第一部分和半导体器件的第二部分（例如，第一晶体管）之间的多晶间隔时，半导体器件包括高度与长度之比超过至少1.6的源极或漏极中的至少一个 （例如，第二晶体管）小于约60nm。