公开(公告)号：US12009316B2

公开(公告)日：2024-06-11

申请号：US17244800

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsien-Wen Liu ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.

公开(公告)号：US11798898B2

公开(公告)日：2023-10-24

申请号：US17366413

申请日：2021-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao-Wen Lee ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/0223 ,  H01L21/3043 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/18 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L2221/6834 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/118 ,  H01L2224/18

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

公开(公告)号：US11329031B2

公开(公告)日：2022-05-10

申请号：US16995062

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Cheng-Lin Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/10

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

公开(公告)号：US10290590B2

公开(公告)日：2019-05-14

申请号：US15485530

申请日：2017-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shin-Puu Jeng ,  Tzu-Jui Fang ,  Hsi-Kuei Cheng ,  Chih-Kang Han ,  Yi-Jen Lai ,  Hsien-Wen Liu ,  Yi-Jou Lin

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/373 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

公开(公告)号：US10074617B2

公开(公告)日：2018-09-11

申请号：US15376437

申请日：2016-12-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/02 ,  H01L23/31 ,  H01L23/538 ,  H01L23/29 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/564 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/024 ,  H01L2224/03332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

公开(公告)号：US09950450B2

公开(公告)日：2018-04-24

申请号：US14527598

申请日：2014-10-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Jui-Pin Hung ,  Hsien-Wen Liu

IPC: B29C35/08 ,  H05B6/64 ,  H05B6/80 ,  H01L21/56

CPC classification number: B29C35/0805 ,  B29C2035/0855 ,  H01L21/565 ,  H05B6/6491 ,  H05B6/806

Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.

公开(公告)号：US20170170161A1

公开(公告)日：2017-06-15

申请号：US15443827

申请日：2017-02-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/1134 ,  H01L2224/1148 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US10861801B2

公开(公告)日：2020-12-08

申请号：US16696771

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/10 ,  H01L21/02 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

公开(公告)号：US20200381407A1

公开(公告)日：2020-12-03

申请号：US16995062

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Pin Hung ,  Cheng-Lin Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

公开(公告)号：US10354988B2

公开(公告)日：2019-07-16

申请号：US16139660

申请日：2018-09-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wen Liu ,  Yi-Jou Lin

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L21/288 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.