Invention Grant
- Patent Title: Wafer level package (WLP) and method for forming the same
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Application No.: US16696771Application Date: 2019-11-26
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Publication No.: US10861801B2Publication Date: 2020-12-08
- Inventor: Shin-Puu Jeng , Hsien-Wen Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/29 ; H01L23/31 ; H01L25/10 ; H01L21/02 ; H01L23/538 ; H01L23/498

Abstract:
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
Public/Granted literature
- US20200098705A1 Wafer Level Package (WLP) and Method for Forming the Same Public/Granted day:2020-03-26
Information query
IPC分类: