Invention Application
- Patent Title: Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination
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Application No.: US15443827Application Date: 2017-02-27
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Publication No.: US20170170161A1Publication Date: 2017-06-15
- Inventor: Jing-Cheng Lin , Jui-Pin Hung , Hsien-Wen Liu , Min-Chen Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L23/00 ; H01L21/56 ; H01L25/065

Abstract:
An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
Public/Granted literature
- US11081475B2 Integrated circuit structure and method for reducing polymer layer delamination Public/Granted day:2021-08-03
Information query
IPC分类: