Invention Application
- Patent Title: Structure and Formation Method for Chip Package
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Application No.: US16995062Application Date: 2020-08-17
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Publication No.: US20200381407A1Publication Date: 2020-12-03
- Inventor: Jui-Pin Hung , Cheng-Lin Huang , Hsien-Wen Liu , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L21/56 ; H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
Public/Granted literature
- US11329031B2 Structure and formation method for chip package Public/Granted day:2022-05-10
Information query
IPC分类: