公开(公告)号：US11756928B2

公开(公告)日：2023-09-12

申请号：US17726545

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5383 ,  H01L25/16 ,  H01L25/50 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2225/06517 ,  H01L2225/06548

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US11342306B2

公开(公告)日：2022-05-24

申请号：US17006863

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US11798898B2

公开(公告)日：2023-10-24

申请号：US17366413

申请日：2021-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsiao-Wen Lee ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/0223 ,  H01L21/3043 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/18 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L2221/6834 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/118 ,  H01L2224/18

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

公开(公告)号：US10797007B2

公开(公告)日：2020-10-06

申请号：US16201187

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiao-Wen Lee ,  Hsiu-Mei Yu

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

Abstract: The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.

公开(公告)号：US20230369287A1

公开(公告)日：2023-11-16

申请号：US18354632

申请日：2023-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/0652 ,  H01L25/16 ,  H01L23/5383 ,  H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L2225/06548 ,  H01L2225/06517 ,  H01L2221/68345 ,  H01L23/3128

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US20220246579A1

公开(公告)日：2022-08-04

申请号：US17726545

申请日：2022-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.