公开(公告)号：US20140327151A1

公开(公告)日：2014-11-06

申请号：US14334100

申请日：2014-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ku-Feng YANG ,  Tsang-Jiuh WU ,  Yi-Hsiu CHEN ,  Ebin LIAO ,  Yuan-Hung LIU ,  Wen-Chih CHIOU

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.

摘要翻译： 一种结构包括衬底和衬底上的互连结构。 该结构还包括延伸穿过互连结构并进入衬底的贯穿衬底通孔（TSV），TSV包括导电材料层。 该结构还包括介电层，其具有互连结构上的第一部分和TSV内的第二部分，其中第一部分和第二部分包括相同的材料。 导电材料层包括通过介电层的第二部分与衬底分离的第一部分。 导电材料层还包括在电介质层的第二部分的顶表面上的第二部分。 导电材料层还包括在第二部分上的第三部分，其中第三部分具有大于第二部分的宽度的宽度。

公开(公告)号：US20140130962A1

公开(公告)日：2014-05-15

申请号：US14157210

申请日：2014-01-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO ,  Wen-Chih CHIOU ,  Shin-Puu JENG ,  Hung-Jung TU

IPC分类号： H01L21/02

CPC分类号： H01L21/02057 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/10 ,  Y10T156/1153 ,  Y10T156/1158

摘要： A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.

摘要翻译： 一种方法包括接收其上形成有释放层的载体。 第一粘合剂层形成在晶片上。 第二粘合剂层形成在第一粘合剂层上或剥离层上方。 载体和晶片与载体和晶片之间的剥离层，第一粘合剂层和第二粘合剂层结合。

公开(公告)号：US20240128211A1

公开(公告)日：2024-04-18

申请号：US18308032

申请日：2023-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  An-Jhih SU ,  Hua-Wei TSENG ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  Chun-Wei CHEN ,  Ming Shih YEH ,  Wei-Cheng WU ,  Der-Chyang YEH

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L24/05 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/08225 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/83097 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3512 ,  H01L2924/3841

摘要： Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

公开(公告)号：US20190067107A1

公开(公告)日：2019-02-28

申请号：US16168306

申请日：2018-10-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/3105 ,  H01L23/498 ,  H01L21/321 ,  H01L21/306 ,  H01L21/02

摘要： A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

公开(公告)号：US20140015146A1

公开(公告)日：2014-01-16

申请号：US14033862

申请日：2013-09-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L23/498

CPC分类号： H01L21/76898 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/30625 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/481 ,  H01L23/49827 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate having an opening A first dielectric liner having a first compressive stress is disposed in the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner.

摘要翻译： 半导体部件包括具有开口的半导体衬底。具有第一压缩应力的第一电介质衬垫设置在开口中。 具有拉伸应力的第二电介质衬垫设置在第一电介质衬垫上。 具有设置在第二电介质衬垫上的第二压缩应力的第三绝缘衬垫。

公开(公告)号：US20240107780A1

公开(公告)日：2024-03-28

申请号：US18150569

申请日：2023-01-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  An-Jhih SU ,  Chia-Nan YUAN

IPC分类号： H10B80/00 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48

CPC分类号： H10B80/00 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/08265 ,  H01L2224/119 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193

摘要： A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.

公开(公告)号：US20150228541A1

公开(公告)日：2015-08-13

申请号：US14692799

申请日：2015-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yuan-Hung LIU ,  Ku-Feng YANG ,  Pei-Ching KUO ,  Ming-Tsu CHUNG ,  Hsin-Yu CHEN ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes forming at least one opening through a first surface of a substrate. The method further includes forming at least one conductive structure in the at least one opening. The method further includes removing a portion of the substrate to form a processed substrate having the first surface and a second surface opposite the first surface and to expose a portion of the at least one conductive structure adjacent to the second surface. The at least one conductive structure continuously extending from the first surface through the processed substrate to the second surface of the processed substrate, at least one sidewall of the at least one conductive structure spaced from a sidewall of the at least one opening by an air gap.

摘要翻译： 形成集成电路的方法包括通过衬底的第一表面形成至少一个开口。 该方法还包括在至少一个开口中形成至少一个导电结构。 该方法还包括去除衬底的一部分以形成具有第一表面的处理衬底和与第一表面相对的第二表面，并且暴露出与第二表面相邻的至少一个导电结构的一部分。 所述至少一个导电结构从所述第一表面延续经处理的衬底到所述经处理衬底的所述第二表面，所述至少一个导电结构的至少一个侧壁与所述至少一个开口的侧壁间隔开一气隙 。

公开(公告)号：US20130224909A1

公开(公告)日：2013-08-29

申请号：US13854230

申请日：2013-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Weng-Jin WU ,  Yung-Chi LIN ,  Wen-Chih CHIOU

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening.

摘要翻译： 在一个过程中，形成从半导体衬底的前表面延伸穿过半导体衬底的至少一部分的开口。 金属种子层形成在开口的侧壁上。 在金属种子层的至少一部分上形成金属硅化物层。 在金属硅化物层和金属种子层上形成金属层以填充开口。

公开(公告)号：US20240136199A1

公开(公告)日：2024-04-25

申请号：US18099357

申请日：2023-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Chi LIN ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L21/311 ,  H01L21/027 ,  H01L21/033 ,  H01L21/67

CPC分类号： H01L21/31144 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/67069 ,  H01L21/67075

摘要： A semiconductor device and a semiconductor manufacturing method thereof are provided. The semiconductor manufacturing method includes the following streps. A first semiconductor element with a first bonding film is formed. The first bonding film is formed on a first side of the first semiconductor element. The first semiconductor element and the first bonding film form a taper structure. The first bonding film forms a wide portion of the taper structure. The first semiconductor element forms a narrow portion of the taper structure. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film. An oxide layer is filled to surround the first semiconductor element and the first bonding film.

公开(公告)号：US20210005515A1

公开(公告)日：2021-01-07

申请号：US17021600

申请日：2020-09-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Hua YU ,  Cheng-Hung CHANG ,  Ebin LIAO ,  Chia-Lin YU ,  Hsiang-Yi WANG ,  Chun Hua CHANG ,  Li-Hsien HUANG ,  Darryl KUO ,  Tsang-Jiuh WU ,  Wen-Chih CHIOU

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321

摘要： A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T1 at a first end of the opening, and a thickness T2 at a second end of the opening, and R1 is a ratio of T1 to T2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T3 at the first end of the opening, a thickness T4 at the second end of the opening, R2 is a ratio of T3 to T4, and R1 is greater than R2.