公开(公告)号：US11749616B2

公开(公告)日：2023-09-05

申请号：US16042661

申请日：2018-07-23

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K Koduri

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/95 ,  H01L2224/03318 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/0508 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1191 ,  H01L2224/11312 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/1357 ,  H01L2224/1368 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13618 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17107 ,  H01L2224/32227 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/04953 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/13669 ,  H01L2924/00014 ,  H01L2224/13666 ,  H01L2924/00014 ,  H01L2224/13681 ,  H01L2924/00014 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2224/13657 ,  H01L2924/00014 ,  H01L2224/13618 ,  H01L2924/00014 ,  H01L2224/1368 ,  H01L2924/00014

Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

公开(公告)号：US20230260941A1

公开(公告)日：2023-08-17

申请号：US17663328

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Yu-Hsiung Wang ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/7684 ,  H01L21/76898 ,  H01L21/76816 ,  H01L21/76807 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05647 ,  H01L2224/05546 ,  H01L2224/05573 ,  H01L2224/05006 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.

公开(公告)号：US09911707B2

公开(公告)日：2018-03-06

申请号：US14253170

申请日：2014-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L24/13 ,  H01L21/76807 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/01014 ,  H01L2224/05552

Abstract: An integrated circuit structure includes a substrate, and a first metal layer over the substrate. The integrated circuit structure further includes a second insulating layer over the first metal layer, the second insulating layer having a damascene opening and two via openings. The damascene opening has a first depth. The two via openings have a second depth greater than the first depth. The integrated circuit structure further includes a stress buffer having a flat upper surface extending from a first side of the stress buffer to a second side of the stress buffer, the first side and second side being parallel, the stress buffer having a thickness between the upper surface of the stress buffer and the first metal layer, the thickness being less than the second depth and greater than the first depth. The integrated circuit structure further includes a second metal layer over the stress buffer.

公开(公告)号：US09646882B2

公开(公告)日：2017-05-09

申请号：US15261343

申请日：2016-09-09

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/66 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/522 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76883 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/5382 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05026 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/8012 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81097 ,  H01L2224/81099 ,  H01L2224/81208 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81

Abstract: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close undesirable opens or voids between contacts of the two integrated circuits.

公开(公告)号：US09490212B2

公开(公告)日：2016-11-08

申请号：US12798173

申请日：2010-03-31

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/532 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5329 ,  H01L21/76807 ,  H01L23/481 ,  H01L23/522 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05026 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/8012 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81097 ,  H01L2224/81099 ,  H01L2224/81208 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

Abstract: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close or eliminate undesirable opens or voids between two integrated circuits.

Abstract translation: 公开了通过Z字形导电链将3D布置中的至少两个集成电路连接起来的方法和结构。 在晶片接合工艺中用作弹簧或自适应接触结构（SACS）的之字形导电链被设计为减少接合界面应力，增加键合界面的可靠性，以及具有可调整的高度以封闭或消除不需要的开口 或两个集成电路之间的空隙。

公开(公告)号：US09287225B2

公开(公告)日：2016-03-15

申请号：US14191308

申请日：2014-02-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kenro Nakamura ,  Hirokazu Ezawa

IPC: H01L21/302 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/535 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05026 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11616 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

Abstract translation: 一种制造半导体器件的方法包括在第一衬底中形成开口并用金属填充开口以形成第一连接电极。 然后通过化学机械抛光在使得金属的抛光速率小于金属周围区域的条件下抛光第一衬底。 化学机械抛光使第一连接电极从第一基板的表面突出。 第一衬底与具有第二连接电极的第二衬底层叠。 通过施加压力和加热将第一和第二连接电极接合到低于第一连接电极的金属的熔点的温度。

公开(公告)号：US09263382B2

公开(公告)日：2016-02-16

申请号：US14334100

申请日：2014-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A structure includes a substrate, and an interconnect structure over the substrate. The structure further includes a through-substrate-via (TSV) extending through the interconnect structure and into the substrate, the TSV comprising a conductive material layer. The structure further includes a dielectric layer having a first portion over the interconnect structure and a second portion within the TSV, wherein the first portion and the second portion comprise a same material. The conductive material layer includes a first section separated from substrate by the second portion of the dielectric layer. The conductive material layer further includes a second section over a top surface of the second portion of the dielectric layer. The conductive material layer further includes a third section over the second section, wherein the third section has a width greater than a width of the second section.

Abstract translation: 一种结构包括衬底和衬底上的互连结构。 该结构还包括延伸穿过互连结构并进入衬底的贯穿衬底通孔（TSV），TSV包括导电材料层。 该结构还包括介电层，其具有互连结构上的第一部分和TSV内的第二部分，其中第一部分和第二部分包括相同的材料。 导电材料层包括通过介电层的第二部分与衬底分离的第一部分。 导电材料层还包括在电介质层的第二部分的顶表面上的第二部分。 导电材料层还包括在第二部分上的第三部分，其中第三部分具有大于第二部分的宽度的宽度。

公开(公告)号：US09190347B2

公开(公告)日：2015-11-17

申请号：US13967165

申请日：2013-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jen Lai ,  You-Hua Chou ,  Hon-Lin Huang ,  Huai-Tei Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.

Abstract translation: 提供了利用芯片边缘触点的半导体器件。 集成电路管芯具有后钝化层，其具有填充有从接触件延伸到管芯边缘的导电材料的沟槽，从而形成管芯边缘接触。 可选地，贯穿衬底通孔可以沿着管芯边缘定位，使得沟槽中的导电材料电连接到贯穿衬底通孔，从而形成更大的管芯边缘接触。 集成电路管芯可以放置在多管芯封装中，其中多管芯封装包括具有垂直于集成电路管芯的主表面的主表面的壁。 模边缘触点电耦合到多模封装的壁上的触点。 多管芯封装可以包括用于连接到另一衬底的边缘触点，例如印刷电路板，封装衬底，高密度互连等。

公开(公告)号：US08922019B2

公开(公告)日：2014-12-30

申请号：US14069282

申请日：2013-10-31

Applicant: Internatinoal Business Machines Corporation

Inventor： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna W. Semkow

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Disclosed is a semiconductor device wherein an insulation layer has a via opening with an aluminum layer in the via opening and in contact with the last wiring layer of the device. There is a barrier layer on the aluminum layer followed by a copper plug which fills the via opening. Also disclosed is a process for making the semiconductor device.

Abstract translation: 公开了一种半导体器件，其中绝缘层在通孔开口中具有铝层的通孔，并与器件的最后布线层接触。 在铝层上有阻挡层，其后是填充通孔的铜塞。 还公开了制造半导体器件的方法。

公开(公告)号：US20140225253A1

公开(公告)日：2014-08-14

申请号：US14253170

申请日：2014-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsien-Wei CHEN ,  Ying-Ju CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/76807 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2924/01014 ,  H01L2224/05552

Abstract: An integrated circuit structure includes a substrate, and a first metal layer over the substrate. The integrated circuit structure further includes a second insulating layer over the first metal layer, the second insulating layer having a damascene opening and two via openings. The damascene opening has a first depth. The two via openings have a second depth greater than the first depth. The integrated circuit structure further includes a stress buffer having a flat upper surface extending from a first side of the stress buffer to a second side of the stress buffer, the first side and second side being parallel, the stress buffer having a thickness between the upper surface of the stress buffer and the first metal layer, the thickness being less than the second depth and greater than the first depth. The integrated circuit structure further includes a second metal layer over the stress buffer.

Abstract translation: 集成电路结构包括衬底和衬底上的第一金属层。 集成电路结构还包括在第一金属层上的第二绝缘层，第二绝缘层具有镶嵌开口和两个通孔。 镶嵌开口具有第一深度。 两个通孔开口具有大于第一深度的第二深度。 所述集成电路结构还包括应力缓冲器，其具有从应力缓冲器的第一侧延伸到所述应力缓冲器的第二侧的平坦的上表面，所述第一侧和第二侧是平行的，所述应力缓冲器具有在所述上部 应力缓冲区和第一金属层的表面，其厚度小于第二深度并且大于第一深度。 集成电路结构还包括在应力缓冲器上的第二金属层。