公开(公告)号：US20240387192A1

公开(公告)日：2024-11-21

申请号：US18788802

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ching HSU ,  Yu-Huan CHEN ,  Chen-Shien CHEN

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a pad and a conductive adhesive layer over the pad and having a first inner wall, a second inner wall, a first sidewall, and a second sidewall. The first inner wall and the second inner wall face each other, and the first sidewall and the second sidewall are opposite to each other. The chip package structure also includes a nickel layer over the conductive adhesive layer, and the nickel layer covers the first inner wall, the second inner wall, the first sidewall, and the second sidewall of the conductive adhesive layer. The chip package structure further includes a chip over the wiring substrate and a conductive bump connected between the nickel layer and the chip.

公开(公告)号：US20240120277A1

公开(公告)日：2024-04-11

申请号：US18543110

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hong-Seng SHUE ,  Sheng-Han TSAI ,  Kuo-Chin CHANG ,  Mirng-Ji LII ,  Kuo-Ching HSU

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02235 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0805 ,  H01L2224/08052 ,  H01L2224/081 ,  H01L2224/08113 ,  H01L2224/16104

Abstract: A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.

公开(公告)号：US20240312900A1

公开(公告)日：2024-09-19

申请号：US18675785

申请日：2024-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Huan CHEN ,  Kuo-Ching HSU ,  Chen-Shien CHEN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49866 ,  H01L21/4846 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16145 ,  H01L2224/81911 ,  H01L2224/81912

Abstract: A chip package structure is provided. The chip package structure includes a first wiring substrate comprising a substrate, a first pad, a second pad, and an insulating layer. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, the first surface is opposite to the second surface, the insulating layer is over the first surface and partially covers the first pad, and the first pad is wider than the second pad. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer has a curved surface, and a recess is surrounded by the curved surface and an inner wall of the insulating layer over the first pad.

公开(公告)号：US20240096778A1

公开(公告)日：2024-03-21

申请号：US18513866

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Huei LEE ,  Shu-Shen YEH ,  Kuo-Ching HSU ,  Shyue-Ter LEU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/20645

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

公开(公告)号：US20230016849A1

公开(公告)日：2023-01-19

申请号：US17377620

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Huei LEE ,  Shu-Shen YEH ,  Kuo-Ching HSU ,  Shyue-Ter LEU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC: H01L23/498

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

公开(公告)号：US20220270963A1

公开(公告)日：2022-08-25

申请号：US17744884

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Huan CHEN ,  Kuo-Ching HSU ,  Chen-Shien CHEN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A chip package structure is provided. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a nickel-containing layer over the first pad. The chip package structure includes a conductive protection layer over the nickel-containing layer. The conductive protection layer includes tin, and a recess is surrounded by the conductive protection layer and the insulating layer over the first pad. The chip package structure includes a chip over the second surface of the substrate. The chip package structure includes a conductive bump between the second pad and the chip.

公开(公告)号：US20140014959A1

公开(公告)日：2014-01-16

申请号：US14028673

申请日：2013-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm.

Abstract translation: 封装的IC芯片包括测试焊盘，其中测试焊盘与封装的集成电路芯片中的器件电连接。 封装的IC芯片还包括在测试焊盘的一部分上的第一钝化层，以及覆盖测试焊盘的表面的第二钝化层和围绕测试焊盘的测试区域的第一钝化层的一部分。 覆盖测试垫表面的第二钝化层的边缘与测试垫边缘之间的距离在约2mm至约15mm的范围内。

公开(公告)号：US20230335411A1

公开(公告)日：2023-10-19

申请号：US18341052

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ching HSU ,  Yu-Huan CHEN ,  Chen-Shien CHEN

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81035 ,  H01L2224/81047 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81493

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

公开(公告)号：US20220238352A1

公开(公告)日：2022-07-28

申请号：US17717520

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ching HSU ,  Yu-Huan CHEN ,  Chen-Shien CHEN

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a conductive adhesive layer over the first pad. The conductive adhesive layer is in direct contact with the first pad. The chip package structure includes a nickel layer over the conductive adhesive layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip. The conductive bump includes gold.

公开(公告)号：US20140130962A1

公开(公告)日：2014-05-15

申请号：US14157210

申请日：2014-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO ,  Wen-Chih CHIOU ,  Shin-Puu JENG ,  Hung-Jung TU

IPC: H01L21/02

CPC classification number: H01L21/02057 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/10 ,  Y10T156/1153 ,  Y10T156/1158

Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.

Abstract translation: 一种方法包括接收其上形成有释放层的载体。 第一粘合剂层形成在晶片上。 第二粘合剂层形成在第一粘合剂层上或剥离层上方。 载体和晶片与载体和晶片之间的剥离层，第一粘合剂层和第二粘合剂层结合。