公开(公告)号：US20240371705A1

公开(公告)日：2024-11-07

申请号：US18312012

申请日：2023-05-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jeng-Nan HUNG ,  Chen-Hua YU ,  Tung-Li WU ,  Chung-Jung WU

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L23/00

Abstract: A wafer bonding apparatus is provided. The wafer bonding apparatus includes a first wafer chuck, a second wafer chuck, and a plurality of bonding pins. The first wafer chuck is configured to hold a first wafer. The second wafer chuck is configured to hold a second wafer. The bonding pins are accommodated in the first wafer chuck and configured to be movable through the first wafer chuck to apply pressure to bend the first wafer, thereby causing bonding contact of the first wafer and the second wafer.

公开(公告)号：US20240079381A1

公开(公告)日：2024-03-07

申请号：US18388290

申请日：2023-11-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/60 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/5389 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2924/181

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.

公开(公告)号：US20210265289A1

公开(公告)日：2021-08-26

申请号：US17315921

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Ping CHIANG ,  Yi-Che CHIANG ,  Nien-Fang WU ,  Min-Chien HSIAO ,  Chao-Wen SHIH ,  Shou-Zen CHANG ,  Chung-Shi LIU ,  Chen-Hua YU

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01Q9/04 ,  H01Q21/06 ,  H01Q21/00

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.

公开(公告)号：US20170012019A1

公开(公告)日：2017-01-12

申请号：US15276196

申请日：2016-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Chung-Jung WU ,  Hsiao-Yun CHEN ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Da-Yuan SHIH ,  Chen-Hua YU

IPC: H01L23/00 ,  C22C13/00 ,  B23K35/26 ,  B23K1/00 ,  B23K35/02

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/262 ,  B23K2101/40 ,  B23K2103/08 ,  C22C13/00 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/81947 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3841

Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.

Abstract translation: 一种制造焊料凸点接头的方法包括将包含锡的焊料凸点加热到焊锡凸块的熔化温度以上，其中焊料凸块包括共晶Sn-Bi化合物，并且共晶Sn-Bi化合物不含Ag。 该方法还包括拉伸焊料凸起以增加焊料凸块的高度，其中拉伸焊料凸点形成具有小于90°的接触角的层状结构。 该方法还包括冷却焊料凸块。

公开(公告)号：US20150235873A1

公开(公告)日：2015-08-20

申请号：US14705555

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng WU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU

IPC: H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/565 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/11002 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684

Abstract: A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Abstract translation: 制造封装系统的方法包括在第一衬底的第一表面上形成第一互连结构，在第一衬底中形成至少一个第一穿透硅通孔（TSV）结构，将第一衬底设置在载体上，第一表面 面向载体，在载体上并围绕第一基底沉积模塑复合材料，在第一基底的第二表面上形成第二互连结构，去除载体以在第一基底的第一表面上露出第一互连结构， 以及在所述第一基板的所述第一表面上设置第一集成电路。 第一集成电路通过第一互连结构和连接凸块与至少一个第一TSV结构电耦合。

公开(公告)号：US20140130962A1

公开(公告)日：2014-05-15

申请号：US14157210

申请日：2014-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua YU ,  Kuo-Ching HSU ,  Chen-Shien CHEN ,  Ching-Wen HSIAO ,  Wen-Chih CHIOU ,  Shin-Puu JENG ,  Hung-Jung TU

IPC: H01L21/02

CPC classification number: H01L21/02057 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/10 ,  Y10T156/1153 ,  Y10T156/1158

Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.

Abstract translation: 一种方法包括接收其上形成有释放层的载体。 第一粘合剂层形成在晶片上。 第二粘合剂层形成在第一粘合剂层上或剥离层上方。 载体和晶片与载体和晶片之间的剥离层，第一粘合剂层和第二粘合剂层结合。

公开(公告)号：US20250038073A1

公开(公告)日：2025-01-30

申请号：US18360666

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ke-Han SHEN ,  Chih-Yuan CHEN ,  Jiung WU ,  Hung-Yi Kuo ,  Chung-Ju LEE ,  Tung-He CHOU ,  Ji CUI ,  Kuo-Chung YEE ,  Chen-Hua YU ,  Cheng-Chieh HSIEH ,  Yu-Jen LIEN ,  Yian-Liang KUO ,  Shih-Hao TSENG ,  Jen Yu WANG ,  Tzu-Chieh Chou

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.

公开(公告)号：US20240379738A1

公开(公告)日：2024-11-14

申请号：US18314939

申请日：2023-05-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Ting CHEN ,  Chung-Hao TSAI ,  Chen-Hua YU ,  Chuei-Tang WANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/50

Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

公开(公告)号：US20240203918A1

公开(公告)日：2024-06-20

申请号：US18150949

申请日：2023-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chuei-Tang WANG ,  Tso-Jung CHANG ,  Shih-Ping LIN ,  Jeng-Shien HSIEH ,  Chih-Peng LIN ,  Chieh-Yen CHEN ,  Chen-Hua YU

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

公开(公告)号：US20240114703A1

公开(公告)日：2024-04-04

申请号：US18163412

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu TSAI ,  Szu-Wei LU ,  Shih-Peng TAI ,  Chen-Hua YU

IPC: H10B80/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H10B80/00 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/92125

Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.