公开(公告)号：US20170012019A1

公开(公告)日：2017-01-12

申请号：US15276196

申请日：2016-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Chung-Jung WU ,  Hsiao-Yun CHEN ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Da-Yuan SHIH ,  Chen-Hua YU

IPC: H01L23/00 ,  C22C13/00 ,  B23K35/26 ,  B23K1/00 ,  B23K35/02

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/262 ,  B23K2101/40 ,  B23K2103/08 ,  C22C13/00 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/81947 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3841

Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.

Abstract translation: 一种制造焊料凸点接头的方法包括将包含锡的焊料凸点加热到焊锡凸块的熔化温度以上，其中焊料凸块包括共晶Sn-Bi化合物，并且共晶Sn-Bi化合物不含Ag。 该方法还包括拉伸焊料凸起以增加焊料凸块的高度，其中拉伸焊料凸点形成具有小于90°的接触角的层状结构。 该方法还包括冷却焊料凸块。

公开(公告)号：US20150021755A1

公开(公告)日：2015-01-22

申请号：US14511051

申请日：2014-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Li HSIAO ,  Li-Yen LIN ,  Chih-Hang TUNG

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/44 ,  H01L23/473 ,  H01L23/00 ,  H01L23/053

CPC classification number: H01L25/0657 ,  F28D15/02 ,  H01L23/053 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/473 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/175 ,  H01L2224/17515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/01029 ,  H01L2924/0715 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/014

Abstract: A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

Abstract translation: 堆叠的封装包括衬底和结合到衬底的第一结构。 第一结构具有多个凸块，第一亲水涂层位于第一结构的侧壁上。 堆叠的封装还包括结合到多个凸块的第二结构。 第一亲水涂层位于第二结构的侧壁上。 第一结构在第二结构和衬底之间。 堆叠的包装还包括壳体，其中壳体限定包围第一结构和第二结构的体积。 第二亲水涂层位于壳体内表面的侧壁上。 堆叠的包装还包括在包围第一结构和第二结构的体积内的冷却流体。 冷却流体的顶表面在第二结构的顶表面之上。

公开(公告)号：US20240387447A1

公开(公告)日：2024-11-21

申请号：US18318240

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Geng-Ming CHANG ,  Chih-Hang TUNG ,  Chen-Hua YU ,  Kuo-Chung Yee ,  Kewei ZUO ,  Shou-Yi Wang ,  Tzu-Cheng LIN ,  Shih-Wei LIANG

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065

Abstract: A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

公开(公告)号：US20210375724A1

公开(公告)日：2021-12-02

申请号：US17402920

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Liang SHAO ,  Wen-Lin SHIH ,  Su-Chun YANG ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

公开(公告)号：US20180108632A1

公开(公告)日：2018-04-19

申请号：US15837403

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

公开(公告)号：US20240145316A1

公开(公告)日：2024-05-02

申请号：US18298206

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Jung WU ,  Jeng-Nan HUNG ,  Chih-Hang TUNG

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/822

CPC classification number: H01L22/26 ,  H01L21/67253 ,  H01L21/8221

Abstract: A bonding tool includes a bonding monitoring system. The bonding monitoring system may include one or more sensors that are configured to generate bonding wave propagation data associated with a bonding operation. As a bond between a top semiconductor substrate and a bottom semiconductor substrate propagates from respective centers to respective perimeters of the top semiconductor substrate and the bottom semiconductor substrate, the one or more sensors of the bonding monitoring system generates the bonding wave propagation data. A controller that communicates with the one or more sensors receives the bonding wave propagation data from the one or more sensors. The controller may monitor the bonding wave propagation based on the bonding wave propagation data and/or may determine various performance parameters of the bonding operation, such as a bonding wave propagation rate and/or a bonding wave propagation uniformity, among other examples.

公开(公告)号：US20240096825A1

公开(公告)日：2024-03-21

申请号：US18166116

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua YU ,  Chih-Hang TUNG ,  Kuo-Chung YEE ,  Yian-Liang KUO ,  Jiun-Yi WU

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/04

CPC classification number: H01L24/02 ,  H01L21/56 ,  H01L25/04 ,  H01L2224/02185 ,  H01L2224/03312

Abstract: A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.

公开(公告)号：US20150079763A1

公开(公告)日：2015-03-19

申请号：US14554354

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

Abstract translation: 晶圆级牵引方法包括将顶部保持器固定到多个芯片; 以及将底部保持器固定到晶片上，其中所述多个芯片通过多个焊料凸块接合到所述晶片。 晶片级牵引方法还包括软化多个焊料凸块; 并且拉伸多个软化的焊料凸块。

公开(公告)号：US20210384103A1

公开(公告)日：2021-12-09

申请号：US17411579

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Liang SHAO ,  Jen-Yu WANG ,  Chung-Jung WU ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18

Abstract: A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

公开(公告)号：US20210335750A1

公开(公告)日：2021-10-28

申请号：US17366446

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hang TUNG ,  Tung-Liang SHAO ,  Su-Chun YANG ,  Geng-Ming CHANG ,  Chen-Hua YU

IPC: H01L23/00

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.