公开(公告)号：US20150079763A1

公开(公告)日：2015-03-19

申请号：US14554354

申请日：2014-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

Abstract translation: 晶圆级牵引方法包括将顶部保持器固定到多个芯片; 以及将底部保持器固定到晶片上，其中所述多个芯片通过多个焊料凸块接合到所述晶片。 晶片级牵引方法还包括软化多个焊料凸块; 并且拉伸多个软化的焊料凸块。

公开(公告)号：US20210375724A1

公开(公告)日：2021-12-02

申请号：US17402920

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Liang SHAO ,  Wen-Lin SHIH ,  Su-Chun YANG ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

公开(公告)号：US20180108632A1

公开(公告)日：2018-04-19

申请号：US15837403

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/11 ,  B23K1/0016 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11848 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/75252 ,  H01L2224/75317 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75843 ,  H01L2224/7598 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2224/81 ,  H01L2924/00

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices.

公开(公告)号：US20240128178A1

公开(公告)日：2024-04-18

申请号：US18166122

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung LIN ,  Wei-Ming WANG ,  Su-Chun YANG ,  Jih-Churng TWU ,  Shih-Peng TAI ,  Kuo-Chung YEE

IPC: H01L23/498 ,  H01L21/762 ,  H01L23/29

CPC classification number: H01L23/49827 ,  H01L21/76224 ,  H01L23/298

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

公开(公告)号：US20170012019A1

公开(公告)日：2017-01-12

申请号：US15276196

申请日：2016-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Su-Chun YANG ,  Chung-Jung WU ,  Hsiao-Yun CHEN ,  Yi-Li HSIAO ,  Chih-Hang TUNG ,  Da-Yuan SHIH ,  Chen-Hua YU

IPC: H01L23/00 ,  C22C13/00 ,  B23K35/26 ,  B23K1/00 ,  B23K35/02

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/262 ,  B23K2101/40 ,  B23K2103/08 ,  C22C13/00 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16506 ,  H01L2224/16507 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8193 ,  H01L2224/81947 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3841

Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.

Abstract translation: 一种制造焊料凸点接头的方法包括将包含锡的焊料凸点加热到焊锡凸块的熔化温度以上，其中焊料凸块包括共晶Sn-Bi化合物，并且共晶Sn-Bi化合物不含Ag。 该方法还包括拉伸焊料凸起以增加焊料凸块的高度，其中拉伸焊料凸点形成具有小于90°的接触角的层状结构。 该方法还包括冷却焊料凸块。

公开(公告)号：US20210335750A1

公开(公告)日：2021-10-28

申请号：US17366446

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hang TUNG ,  Tung-Liang SHAO ,  Su-Chun YANG ,  Geng-Ming CHANG ,  Chen-Hua YU

IPC: H01L23/00

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution layer having a bonding portion. The bonding portion includes a dielectric layer. The chip package structure includes a chip structure bonded to the bonding portion. A first width of the dielectric layer of the bonding portion is substantially equal to a second width of the chip structure. The chip package structure includes a protective layer over the first redistribution layer and surrounding the chip structure. A portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion.