公开(公告)号：US20240404909A1

公开(公告)日：2024-12-05

申请号：US18327179

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung LIN ,  Shih-Peng TAI ,  Yu-Yi HUANG ,  Yu-Hao KUO

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A method for forming a package structure is provided, wherein the method includes forming an interconnect structure in a substrate. The method also includes bonding a chip over the substrate and electrically connected to the interconnect structure. The method includes bonding a plurality of dies over the substrate and adjacent to the chip. The method also includes supplying a molding material to the gap between the chip and the dies, after which the method includes thinning down the substrate.

公开(公告)号：US20250052966A1

公开(公告)日：2025-02-13

申请号：US18447835

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Yi HUANG ,  Yu-Hao KUO ,  Chiao-Chun CHANG ,  Jui-Hsuan TSAI ,  Yu-Hung LIN ,  Shih-Peng TAI ,  Jih-Churng TWU ,  Chen-Hua YU

IPC: G02B6/42

Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

公开(公告)号：US20240114703A1

公开(公告)日：2024-04-04

申请号：US18163412

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Fu TSAI ,  Szu-Wei LU ,  Shih-Peng TAI ,  Chen-Hua YU

IPC: H10B80/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H10B80/00 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/92 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/92125

Abstract: A package structure and a formation method are provided. The method includes providing a semiconductor substrate and bonding a first chip structure on the semiconductor substrate through metal-to-metal bonding and dielectric-to-dielectric bonding. The method also includes bonding a second chip structure over the semiconductor substrate through solder-containing bonding structures. The method further includes forming a protective layer surrounding the second chip structure. A portion of the protective layer is between the semiconductor substrate and a bottom of the second chip structure.

公开(公告)号：US20240113034A1

公开(公告)日：2024-04-04

申请号：US18166109

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung LIN ,  Wei-Ming WANG ,  Chih-Hao YU ,  PaoTai HUANG ,  Pei-Hsuan LO ,  Shih-Peng TAI

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05025

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first alignment mark in a first substrate of a first wafer and forming a first bonding structure over the first substrate. The method also includes forming a second bonding structure over a second substrate of a second wafer and trimming the second substrate, so that a first width of the first substrate is greater than a second width of the second substrate. The method further includes attaching the second wafer to the first wafer via the first bonding structure and the second bonding structure, thinning the second wafer until a through-substrate via in the second substrate is exposed, and performing a photolithography process on the second wafer using the first alignment mark.

公开(公告)号：US20250004202A1

公开(公告)日：2025-01-02

申请号：US18343388

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Ming WANG ,  Chen CHEN ,  Chih-Hao YU ,  Shih-Peng TAI

IPC: G02B6/13

Abstract: A method of forming a semiconductor package is provided. The method includes forming a first wafer that includes multiple photonic dies. The method includes forming a second wafer that includes multiple electronic dies. The method includes forming micro lenses within the second wafer. The method includes bonding the first wafer to the second wafer after forming the plurality of micro lenses. The method further includes performing a singulation process to dice the first wafer and the second wafer to form multiple photonic packages, wherein one of the photonic packages includes an electronic die, a photonic die bonded to the electronic die, and one or more micro lenses embedded in the electronic die.

公开(公告)号：US20240128178A1

公开(公告)日：2024-04-18

申请号：US18166122

申请日：2023-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung LIN ,  Wei-Ming WANG ,  Su-Chun YANG ,  Jih-Churng TWU ,  Shih-Peng TAI ,  Kuo-Chung YEE

IPC: H01L23/498 ,  H01L21/762 ,  H01L23/29

CPC classification number: H01L23/49827 ,  H01L21/76224 ,  H01L23/298

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

公开(公告)号：US20240118491A1

公开(公告)日：2024-04-11

申请号：US18099059

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao YU ,  Jui Lin CHAO ,  Hsing-Kuo HSIA ,  Shih-Peng TAI ,  Kuo-Chung YEE

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B6/13 ,  G02B2006/12121

Abstract: A photonic semiconductor device including a light-emitting component and a photonic integrated circuit is provided. The light-emitting component at least includes a gain medium layer, a first contact layer and a first optical coupling layer stacked to each other. The photonic integrated circuit includes a second optical coupling layer. The light-emitting component and the photonic integrated circuit are stacked in a stacking direction, the first optical coupling layer has a first taper portion, the second optical coupling layer has a second taper portion, and the first taper portion and the second taper portion overlap in the stacking direction. Accordingly, the light emitted from the gain medium layer may be transmitted to the second taper portion from the first taper portion by optical coupling in a short length of an optical coupling path.