-
公开(公告)号：US20240371828A1
公开(公告)日：2024-11-07
申请号：US18772307
申请日：2024-07-15
Inventor： Chuei-Tang WANG , Chien-Yuan Huang , Shih-Chang Ku
IPC: H01L25/065 , H01L23/00
Abstract: Disclosed are a semiconductor stack structure and a manufacturing method of a semiconductor stack structure. In one embodiment, the semiconductor stack structure includes a first semiconductor element, a second semiconductor element side-by-side bonded to the first semiconductor element through a direct bonding manner and a third semiconductor element, wherein the first semiconductor element and the second semiconductor element are bonded on the third semiconductor element.
-
公开(公告)号：US20240404900A1
公开(公告)日：2024-12-05
申请号：US18326485
申请日：2023-05-31
Inventor： Chuei-Tang WANG , Tso-Jung CHANG , Jeng-Shien HSIEH , Chih-Peng LIN , Chieh-Yen CHEN , Chen-Hua YU
Abstract: A method for forming a semiconductor package is provided. The method includes forming a first photonic routing structure over a substrate, disposing the first photonic routing structure over a redistribution structure, disposing a second photonic routing structure and an optical engine die on the redistribution structure and forming a molding structure between and separating the first photonic routing structure and the second photonic routing structure.
-
公开(公告)号：US20240387493A1
公开(公告)日：2024-11-21
申请号：US18786583
申请日：2024-07-29
Inventor： Chih-Chieh Chang , Chung-Hao Tsai , Chen-Hua Yu , Chuei-Tang WANG
Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad. First conductive pad is connected to through semiconductor via. Emission region directly faces sidewall of recess where edge coupler is located.
-
公开(公告)号：US20240387329A1
公开(公告)日：2024-11-21
申请号：US18320398
申请日：2023-05-19
Inventor： Chih-Hsin LU , Chia-Chia LIN , Ching-Ho CHIN , Chung-Hao TSAI , Chuei-Tang WANG , Chen-Hua YU
IPC: H01L23/48 , G02B6/122 , H01L21/768 , H01L23/498 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.
-
公开(公告)号：US20240206193A1
公开(公告)日：2024-06-20
申请号：US18151742
申请日：2023-01-09
Inventor： Chuei-Tang WANG , Tso-Jung CHANG , Wen-Shiang LIAO , Jeng-Shien HSIEH , Chih-Peng LIN , Shih-Ping LIN , Chieh-Yen CHEN , Chen-Hua YU
IPC: H10B80/00 , H01L23/00 , H01L23/31 , H01L23/538
CPC classification number: H10B80/00 , H01L23/3128 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2924/15311
Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.
-
Patent Agency Ranking
公开(公告)号：US20240047365A1
公开(公告)日：2024-02-08
申请号：US18150539
申请日：2023-01-05
Inventor： Chuei-Tang WANG , Tso-Jung CHANG , Jeng-Shien HSIEH , Shih-Ping LIN , Chieh-Yen CHEN , Chen-Hua YU
IPC: H01L23/538 , H01L23/00 , H01L25/065 , H01L21/48
CPC classification number: H01L23/5386 , H01L24/13 , H01L24/08 , H01L24/80 , H01L25/0652 , H01L21/4857 , H01L21/486 , H01L23/5383 , H01L2224/13023 , H01L2224/08235 , H01L2224/08146 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/182
Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
-
公开(公告)号：US20160104940A1
公开(公告)日：2016-04-14
申请号：US14510796
申请日：2014-10-09
Inventor： Chuei-Tang WANG , Jeng-Shieh HSIEH , Chung-Hao TSAI , Monsen LIU , Chen-Hua YU
IPC: H01Q19/10 , H01Q19/185 , H01Q19/00
CPC classification number: H01Q21/065 , H01L23/66 , H01L24/20 , H01L2223/6677 , H01L2224/04105 , H01L2224/12105 , H01Q1/2283 , H01Q19/005 , H01Q19/10 , H01Q19/185
Abstract: An integrated fan out (InFO) antenna includes a reflector on a surface of a substrate; and a package. The package includes a redistribution layer (RDL) arranged to form an antenna ground, and a patch antenna over the RDL, wherein the RDL is between the patch antenna and the reflector. The InFO antenna further includes a plurality of connecting elements bonding the package to the reflector. Each connecting element of the plurality of connecting elements is located inside an outer perimeter of the reflector. The InFO antenna is configured to output a signal having a wavelength.
Abstract translation: 集成的风扇输出（InFO）天线包括在基板的表面上的反射器; 和一个包。 该封装包括布置成形成天线接地的再分配层（RDL）和RDL上的贴片天线，其中RDL位于贴片天线和反射器之间。 InFO天线还包括将封装结合到反射器的多个连接元件。 多个连接元件的每个连接元件位于反射器的外周边内。 InFO天线被配置为输出具有波长的信号。
-
公开(公告)号：US20240379738A1
公开(公告)日：2024-11-14
申请号：US18314939
申请日：2023-05-10
Inventor： Wei-Ting CHEN , Chung-Hao TSAI , Chen-Hua YU , Chuei-Tang WANG
IPC: H01L25/065 , H01L23/00 , H01L23/50
Abstract: A package structure and a formation method are provided. The method includes forming a capacitor element over a first chip structure and forming a dielectric layer over the capacitor element. The method also includes forming a conductive bonding structure in the dielectric layer. A top surface of the conductive bonding structure is substantially coplanar with a top surface of the dielectric layer. The conductive bonding structure penetrates through the capacitor element and is electrically connected to the capacitor element. The method further includes bonding a second chip structure to the dielectric layer and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
-
公开(公告)号：US20240203918A1
公开(公告)日：2024-06-20
申请号：US18150949
申请日：2023-01-06
Inventor： Chuei-Tang WANG , Tso-Jung CHANG , Shih-Ping LIN , Jeng-Shien HSIEH , Chih-Peng LIN , Chieh-Yen CHEN , Chen-Hua YU
IPC: H01L23/00
CPC classification number: H01L24/08 , H01L24/80 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896
Abstract: A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.
-
公开(公告)号：US20240088033A1
公开(公告)日：2024-03-14
申请号：US18186206
申请日：2023-03-20
Inventor： Chao-Kai Chan , Chung-Hao Tsai , Chuei-Tang WANG , Wei-Ting Chen
IPC: H01L23/528 , H01L21/8234 , H01L23/522 , H01L29/06 , H01L29/423 , H01L29/94
CPC classification number: H01L23/5283 , H01L21/823412 , H01L21/823475 , H01L23/5226 , H01L29/0673 , H01L29/42392 , H01L29/945
Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.
-
-
-
-
-
-
-
-
-
Search Results
29
records
(took 0.02 seconds)
