公开(公告)号：US20150130072A1

公开(公告)日：2015-05-14

申请号：US14079736

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Wei WU ,  Ying-Ching SHIH ,  Szu-Wei LU ,  Jing-Cheng LIN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: The embodiments described provide methods and structures for forming support structures between dies and substrate(s) of a three dimensional integrated circuit (3DIC) structures. Each support structure adheres to surfaces of two neighboring dies or die and substrate to relieve stress caused by bowing of the die(s) and/or substrate on the bonding structures formed between the dies or die and substrate. The cost of the support structures is much lower than other processes, such as thermal compression bonding, to reduce the effect of bowing of dies and substrates on 3DIC formation. The support structures improves yield of 3DIC structures.

Abstract translation: 所描述的实施例提供了用于在三维集成电路（3DIC）结构的管芯和衬底之间形成支撑结构的方法和结构。 每个支撑结构粘附在两个相邻的模具或模具和基板的表面上，以减轻由在模具或模具和基板之间形成的结合结构上的模具和/或基板弯曲引起的应力。 支撑结构的成本比其他工艺（例如热压接）要低得多，以减少模具和衬底的弯曲对3DIC形成的影响。 支撑结构提高了3DIC结构的产量。

公开(公告)号：US20160204014A1

公开(公告)日：2016-07-14

申请号：US15075729

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Liang LIN ,  Weng-Jin WU ,  Jing-Cheng LIN

IPC: H01L21/683 ,  H01L21/66

CPC classification number: H01L21/6835 ,  H01L21/67092 ,  H01L21/67109 ,  H01L21/6836 ,  H01L22/12 ,  H01L22/26 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of wafer bonding includes bonding a wafer to a carrier in a bonding system. The method further includes measuring thickness profile of the bonded wafer. The method further includes modifying surface contours of at least one of an upper plate or a lower plate of the bonding system during a bonding operation to improve planarity of bonded wafers based on the measured thickness profile, wherein modifying the surface contours of at least one of the upper plate or the lower plate comprises modifying the surface contours using a plurality of height adjusters.

Abstract translation: 晶片接合的方法包括将晶片接合到接合系统中的载体上。 该方法还包括测量接合晶片的厚度分布。 该方法还包括在接合操作期间修改接合系统的上板或下板中的至少一个的表面轮廓，以基于测量的厚度轮廓来改善接合的晶片的平面度，其中修改至少一个的表面轮廓 上板或下板包括使用多个高度调节器修改表面轮廓。

公开(公告)号：US20240222318A1

公开(公告)日：2024-07-04

申请号：US18608296

申请日：2024-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L23/00 ,  B23K1/00 ,  H01L21/768 ,  H01L23/498 ,  B23K101/42

CPC classification number: H01L24/83 ,  B23K1/0016 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841

Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings. A first opening has a first width, a second opening has a second width, smaller than the first width, and a third opening is between the first opening and the second opening and has a third width, different from the first width and the second width. The width is measured in a direction parallel to a top surface of the substrate. The method further includes plating a first conductive material into each opening of the plurality of openings in the photoresist. Plating the first conductive material includes plating of the first conductive material to a first height in the first opening, plating the first conductive material to a second height in the second opening, and plating the first conductive material to a third height in the third opening.

公开(公告)号：US20240079381A1

公开(公告)日：2024-03-07

申请号：US18388290

申请日：2023-11-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/60 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/5389 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2924/181

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.

公开(公告)号：US20170229422A1

公开(公告)日：2017-08-10

申请号：US15497669

申请日：2017-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498

Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width. A second opening is near an edge of the substrate and has a second width smaller than the first width. A third opening is between the first opening and the second opening and has a third width greater than the second width and smaller than the first width. The method further includes plating a conductive material into each opening. Plating the conductive material includes plating the first conductive material in the first opening at a first current density; plating the first conductive material in the second opening at a second current density greater than the first current density; and plating the conductive material in the third opening at a third current density.

公开(公告)号：US20150187605A1

公开(公告)日：2015-07-02

申请号：US14658690

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng LIN ,  Jui-Pin HUNG ,  Nai-Wei LIU ,  Yi-Chao MAO ,  Wan-Ting SHIH ,  Tsan-Hua TUNG

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad.

Abstract translation: 封装半导体器件的方法包括在半导体器件上形成绝缘层，其中半导体器件具有接触焊盘，并且接触焊盘的厚度大于绝缘层的厚度。 该方法还包括形成覆盖半导体器件的模制化合物和半导体器件与相邻半导体器件之间的空间，其中两个半导体器件都在载体晶片上。 该方法还包括通过在接触垫上移除模塑料和绝缘层来平坦化半导体器件的表面。

公开(公告)号：US20150017764A1

公开(公告)日：2015-01-15

申请号：US14503932

申请日：2014-10-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng LIN ,  Chin-Chuan CHANG ,  Jui-Pin HUNG

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

Abstract translation: 形成半导体封装的方法包括在粘合剂层上形成互连结构，其中粘合剂层在载体上。 该方法还包括将半导体管芯放置在互连结构的表面上。 该方法还包括将封装结构放置在互连结构的表面上，其中半导体管芯装配在互连结构和封装结构之间的空间中。 该方法还包括执行回流以将封装结构连接到互连结构。

公开(公告)号：US20220181305A1

公开(公告)日：2022-06-09

申请号：US17680789

申请日：2022-02-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua YU ,  An-Jhih SU ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L23/60 ,  H01L25/10 ,  H01L25/00

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.

公开(公告)号：US20140299985A1

公开(公告)日：2014-10-09

申请号：US14310488

申请日：2014-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Hua YU ,  Jing-Cheng LIN

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13564 ,  H01L2224/1412 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/381

Abstract: A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

Abstract translation: 多芯片封装包括具有多个第一凸块结构的基板。 多个第一凸块结构的第一凸块结构之间的间距在基板的表面上是均匀的。 多芯片封装包括结合到衬底的第一芯片和与衬底结合的第二芯片。 第一芯片包括多个第二凸块结构，并且多个第二凸块结构被结合到多个第一凸块结构的第一组第一凸块结构。 第二芯片包括多个第三凸块结构，并且多个第三凸起结构被结合到多个第一凸块结构的第二组第一凸块结构。 多个第二凸块结构的第二凸块结构之间的间距与多个第三凸块结构中的第三凸起结构之间的间距不同。

公开(公告)号：US20210043547A1

公开(公告)日：2021-02-11

申请号：US17080564

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jing-Cheng LIN

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L27/06 ,  H01L25/065 ,  H01L21/768 ,  H01L21/762

Abstract: Methods for forming a semiconductor device structure are provided. The method includes forming a conductive feature in a first wafer, and forming a first bonding layer over the conductive feature. The method includes forming a second bonding layer over a second wafer, and bonding the first wafer and the second wafer by bonding the first bonding layer and the second bonding layer. The method also includes forming a second transistor in a front-side of the second wafer, and after forming the second transistor in the front-side of the second wafer, forming a first TSV through the second wafer, wherein the first TSV stops at the conductive feature.