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公开(公告)号：US20240120277A1
公开(公告)日：2024-04-11
申请号：US18543110
申请日：2023-12-18
发明人： Hong-Seng SHUE , Sheng-Han TSAI , Kuo-Chin CHANG , Mirng-Ji LII , Kuo-Ching HSU
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522
CPC分类号： H01L23/5283 , H01L23/5226 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L2224/02235 , H01L2224/0224 , H01L2224/02245 , H01L2224/0225 , H01L2224/02255 , H01L2224/023 , H01L2224/0231 , H01L2224/0233 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/0805 , H01L2224/08052 , H01L2224/081 , H01L2224/08113 , H01L2224/16104
摘要： A chip structure is provided. The chip structure includes a substrate, a redistribution layer over the substrate, a bonding pad over the redistribution layer, a shielding pad over the redistribution layer and surrounding the bonding pad, an insulating layer over the redistribution layer and the shielding pad, and a bump over the bonding pad and the insulating layer. The insulating layer includes a first part and a second part surrounded by the first part, the first part has first thickness, the second part has a second thickness, and the first thickness and the second thickness are different.
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2.发明申请Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad 有权具有衬底的封装，嵌入金属轨迹由着陆垫重叠公开(公告)号：US20150200172A1
公开(公告)日：2015-07-16
申请号：US14155949
申请日：2014-01-15
发明人： Mirng-Ji Lii , Yu-Min Liang , Yu-Feng Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/08 , H01L24/13 , H01L24/16 , H01L2224/03914 , H01L2224/0805 , H01L2224/08112 , H01L2224/13017 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16057 , H01L2224/16058 , H01L2224/16059 , H01L2224/16104 , H01L2224/16151 , H01L2224/16238 , H01L2224/81191 , H01L2224/81193 , H01L2224/81345 , H01L2224/81385 , H01L2224/81801 , H01L2224/81815 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.
摘要翻译： 一种实施方案的封装包括安装在集成电路芯片上的导电柱，所述导电柱具有步进形状，部分嵌入基板中的金属迹线，所述金属迹线具有从所述基板突出的焊盘部分，以及焊接特征电耦合 导电柱到金属轨迹的焊盘部分。
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3.发明申请POWER PACKAGE MODULE OF MULTIPLE POWER CHIPS AND METHOD OF MANUFACTURING POWER CHIP UNIT 审中-公开多功率电源的功率封装模块及制造电源芯片的方法公开(公告)号：US20170062386A1
公开(公告)日：2017-03-02
申请号：US15230670
申请日：2016-08-08
发明人： Tao WANG , Zhenqing ZHAO , Kai LU , Zeng LI , Jianhong ZENG
CPC分类号： H01L21/78 , H01L21/54 , H01L23/3142 , H01L23/3178 , H01L24/03 , H01L24/08 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/03009 , H01L2224/05554 , H01L2224/0603 , H01L2224/0805 , H01L2224/085 , H01L2224/37124 , H01L2224/37139 , H01L2224/37144 , H01L2224/37147 , H01L2224/40 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2224/49111 , H01L2224/49113 , H01L2224/73221 , H01L2924/00014 , H01L2924/13055 , H01L2224/05599 , H01L2924/00
摘要： The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel.
摘要翻译： 本公开的实施例涉及多个功率芯片的功率封装模块和制造功率芯片单元的方法。 多个功率芯片的功率封装模块包括：功率芯片单元，包括并联放置的至少两个功率芯片和接合两个功率芯片的焊接部分; 支撑所述功率芯片单元并且包括与所述功率芯片单元电连接的金属层的基板; 以及将基板上的功率芯片单元与周围隔离以密封功率芯片单元的密封层; 接合部和密封层由不同的绝缘材料制成，平行放置的两个功率芯片之间的间隔距离小于或等于预设宽度，并且将接合部分填充在间隙中，绝缘地接合 两个电源芯片并置放置。
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公开(公告)号：US20140145328A1
公开(公告)日：2014-05-29
申请号：US14160136
申请日：2014-01-21
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/03424 , H01L2224/03464 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/0805 , H01L2224/08145 , H01L2224/08225 , H01L2224/11462 , H01L2224/13014 , H01L2224/13017 , H01L2224/13019 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/13669 , H01L2224/1605 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/27003 , H01L2224/273 , H01L2224/27334 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/3205 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/80048 , H01L2224/80121 , H01L2224/80203 , H01L2224/80411 , H01L2224/80439 , H01L2224/80444 , H01L2224/80447 , H01L2224/80464 , H01L2224/80469 , H01L2224/80801 , H01L2224/80903 , H01L2224/81048 , H01L2224/81121 , H01L2224/81191 , H01L2224/81203 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81464 , H01L2224/81469 , H01L2224/81801 , H01L2224/81903 , H01L2224/83048 , H01L2224/83121 , H01L2224/83192 , H01L2224/83204 , H01L2224/8385 , H01L2224/83851 , H01L2224/83862 , H01L2224/9211 , H01L2924/07802 , H01L2924/10253 , H01L2924/12042 , H01L2924/1461 , H01L2924/15747 , H01L2924/15788 , H01L2924/181 , H01L2924/3651 , H01L2924/381 , H01L2924/00 , H01L2924/00014 , H01L2924/01047 , H01L2924/01079 , H01L2924/0665 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/80
摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate hybrid interconnect assemblies, as well as methods of making and using the assemblies. The hybrid assemblies generally include a semiconductor having a die pad disposed thereon, a substrate having a substrate pad disposed thereon, and a polymer layer disposed between the surface of the die pad and the surface of the substrate pad. In addition, at least a portion of the surface of the die pad is metallically bonded to at least a portion of the surface of the substrate pad and at least a portion of the surface of the die pad is chemically bonded to at least a portion of the surface of the substrate pad.
摘要翻译： 本发明的各种实施例提供细间距，芯片到衬底混合互连组件，以及制造和使用组件的方法。 混合组件通常包括其上设置有管芯焊盘的半导体，其上设置有衬底焊盘的衬底以及设置在管芯焊盘的表面和衬底焊盘的表面之间的聚合物层。 此外，芯片焊盘的表面的至少一部分金属地结合到衬底焊盘的表面的至少一部分，并且芯片焊盘的表面的至少一部分化学键合到至少一部分 衬底垫的表面。
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公开(公告)号：US11848270B2
公开(公告)日：2023-12-19
申请号：US16422988
申请日：2019-05-25
发明人： Hong-Seng Shue , Sheng-Han Tsai , Kuo-Chin Chang , Mirng-Ji Lii , Kuo-Ching Hsu
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522
CPC分类号： H01L23/5283 , H01L23/5226 , H01L24/08 , H01L24/09 , H01L24/11 , H01L24/16 , H01L24/17 , H01L2224/023 , H01L2224/0224 , H01L2224/0225 , H01L2224/0231 , H01L2224/0233 , H01L2224/02235 , H01L2224/02245 , H01L2224/02255 , H01L2224/02373 , H01L2224/02381 , H01L2224/0401 , H01L2224/081 , H01L2224/0805 , H01L2224/08052 , H01L2224/08113 , H01L2224/16104
摘要： A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.
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6.发明授权Package having substrate with embedded metal trace overlapped by landing pad 有权具有嵌入金属轨迹的衬底的封装与着陆焊盘重叠公开(公告)号：US09305890B2
公开(公告)日：2016-04-05
申请号：US14155949
申请日：2014-01-15
发明人： Mirng-Ji Lii , Yu-Min Liang , Yu-Feng Chen
IPC分类号： H01L23/488 , H01L23/00
CPC分类号： H01L24/81 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/08 , H01L24/13 , H01L24/16 , H01L2224/03914 , H01L2224/0805 , H01L2224/08112 , H01L2224/13017 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16057 , H01L2224/16058 , H01L2224/16059 , H01L2224/16104 , H01L2224/16151 , H01L2224/16238 , H01L2224/81191 , H01L2224/81193 , H01L2224/81345 , H01L2224/81385 , H01L2224/81801 , H01L2224/81815 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.
摘要翻译： 一种实施方案的封装包括安装在集成电路芯片上的导电柱，所述导电柱具有步进形状，部分嵌入基板中的金属迹线，所述金属迹线具有从所述基板突出的焊盘部分，以及焊接特征电耦合 导电柱到金属轨迹的焊盘部分。
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7.发明授权Package having substrate with embedded metal trace overlapped by landing pad 有权具有嵌入金属轨迹的衬底的封装与着陆焊盘重叠公开(公告)号：US09559076B2
公开(公告)日：2017-01-31
申请号：US15085352
申请日：2016-03-30
发明人： Mirng-Ji Lii , Yu-Min Liang , Yu-Feng Chen
CPC分类号： H01L24/81 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/08 , H01L24/13 , H01L24/16 , H01L2224/03914 , H01L2224/0805 , H01L2224/08112 , H01L2224/13017 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16057 , H01L2224/16058 , H01L2224/16059 , H01L2224/16104 , H01L2224/16151 , H01L2224/16238 , H01L2224/81191 , H01L2224/81193 , H01L2224/81345 , H01L2224/81385 , H01L2224/81801 , H01L2224/81815 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.
摘要翻译： 一种实施方案的封装包括安装在集成电路芯片上的导电柱，所述导电柱具有步进形状，部分嵌入基板中的金属迹线，所述金属迹线具有从所述基板突出的焊盘部分，以及焊接特征电耦合 导电柱到金属轨迹的焊盘部分。
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公开(公告)号：US20160211239A1
公开(公告)日：2016-07-21
申请号：US15085352
申请日：2016-03-30
发明人： Mirng-Ji Lii , Yu-Min Liang , Yu-Feng Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L24/03 , H01L24/08 , H01L24/13 , H01L24/16 , H01L2224/03914 , H01L2224/0805 , H01L2224/08112 , H01L2224/13017 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/16057 , H01L2224/16058 , H01L2224/16059 , H01L2224/16104 , H01L2224/16151 , H01L2224/16238 , H01L2224/81191 , H01L2224/81193 , H01L2224/81345 , H01L2224/81385 , H01L2224/81801 , H01L2224/81815 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.
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