公开(公告)号：US20240128211A1

公开(公告)日：2024-04-18

申请号：US18308032

申请日：2023-04-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei WU ,  An-Jhih SU ,  Hua-Wei TSENG ,  Ying-Ching SHIH ,  Wen-Chih CHIOU ,  Chun-Wei CHEN ,  Ming Shih YEH ,  Wei-Cheng WU ,  Der-Chyang YEH

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L24/05 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0346 ,  H01L2224/0362 ,  H01L2224/05005 ,  H01L2224/05147 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/08225 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/83097 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/3512 ,  H01L2924/3841

摘要： Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.