公开(公告)号：US09425157B2

公开(公告)日：2016-08-23

申请号：US14190360

申请日：2014-02-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Yu-Min Liang ,  Chen-Shien Chen ,  Chung-Shi Liu

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/17 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16013 ,  H01L2224/16104 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17104 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207

摘要： According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

摘要翻译： 根据示例性实施例，提供具有第一区域和第二区域的基板。 基板包括多个焊盘。 每个垫具有垫尺寸。 第一区域中的焊盘尺寸大于第二区域中的焊盘尺寸。

公开(公告)号：US11887955B2

公开(公告)日：2024-01-30

申请号：US17412551

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hui-Min Huang ,  Ming-Da Cheng ,  Chang-Jung Hsueh ,  Wei-Hung Lin ,  Kai Jun Zhan ,  Wan-Yu Chiang

IPC分类号： H01L23/522 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02181 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/11622 ,  H01L2224/13018

摘要： A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

公开(公告)号：US09530762B2

公开(公告)日：2016-12-27

申请号：US14152168

申请日：2014-01-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Tsai-Tsung Tsai ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/19 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48091

摘要： According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.

摘要翻译： 根据示例性实施例，提供半导体封装。 A半导体封装包括至少一个芯片以及与至少一个芯片相邻的至少一个部件，其中所述至少一个芯片和所述至少一个部件被模制在相同的模制体中。

公开(公告)号：US20240274503A1

公开(公告)日：2024-08-15

申请号：US18110009

申请日：2023-02-15

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin

IPC分类号： H01L23/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/42 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/73253 ,  H01L2225/06589

摘要： A semiconductor package includes an interposer module on a package substrate, a thermal interface material (TIM) layer on the interposer module, a TIM layer protection structure on a side surface of the TIM layer and a side surface of the interposer module, and a package lid on the interposer module, the TIM layer and the TIM layer protection structure. A method of forming the semiconductor package may include mounting an interposer module on a package substrate, locating a thermal interface material (TIM) layer on the interposer module, locating a package lid on the interposer module and the TIM layer, and forming a TIM layer protection structure on a side surface of the TIM layer and a side surface of the interposer module, through a filling hole in the package lid.

公开(公告)号：US20240071890A1

公开(公告)日：2024-02-29

申请号：US17898499

申请日：2022-08-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436

摘要： A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

公开(公告)号：US20230378123A1

公开(公告)日：2023-11-23

申请号：US17749200

申请日：2022-05-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hui-Min Huang ,  Kai Jun Zhan ,  Yi Chen Wu ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L23/00 ,  H01J37/32

CPC分类号： H01L24/81 ,  H01L24/75 ,  H01J37/32825 ,  H01J37/3244 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/75302 ,  H01L2224/81895 ,  H01L2224/81204 ,  H01L2224/81092 ,  H01L2224/81097

摘要： A disclosed system is configured to bond a chip to a substrate and includes a chip processing subsystem that is configured to receive the chip and to expose the chip to a first plasma, and a substrate processing subsystem that is configured to receive the substrate and to expose the substrate to a second plasma. The system further includes a bonding subsystem that is configured to align the chip with the substrate, to force the chip and the substrate into direct mechanical contact with one another by application of a compressive force, and to apply heat to at least one of the chip or the substrate. Application of the compressive force and the heat thereby bonds the chip to the substrate. The first and second plasmas may include H2/N2, H2/Ar, H2/He, NH3/N2, NH3/Ar, or NH3/He and the chip and substrate may be maintained in a low oxygen environment.

公开(公告)号：US20240128219A1

公开(公告)日：2024-04-18

申请号：US18530286

申请日：2023-12-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Hui-Min Huang ,  Wei-Hung Lin ,  Kai Jun Zhan ,  Chang-Jung Hsueh ,  Wan-Yu Chiang ,  Ming-Da Cheng

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02181 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/11622 ,  H01L2224/13018

摘要： A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

公开(公告)号：US20240079303A1

公开(公告)日：2024-03-07

申请号：US18303663

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/28 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H05K3/46

CPC分类号： H01L23/49827 ,  H01L23/28 ,  H01L23/3675 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/05 ,  H01L25/0657 ,  H05K3/4626 ,  H01L2224/05008 ,  H01L2924/181 ,  H01L2924/351 ,  H05K2201/068

摘要： A package substrate and a method of fabrication thereof including a hybrid substrate core having different material properties in different portions of the core. A first portion of the hybrid substrate core may have a lower coefficient of thermal expansion (CTE) compared to a second portion of the hybrid substrate core. The CTE of the first portion of the hybrid substrate core may be close to the CTE of semiconductor integrated circuit dies mounted to a first side of the package substrate in an assembled semiconductor package. The CTE of the second portion of the hybrid substrate core may be close to the CTE of a supporting substrate, such as a printed circuit board, to which the semiconductor package is mounted. The package substrate may help to balance stress, such as thermally-induced stress, in the semiconductor package, thereby improving package reliability.

公开(公告)号：US20240063128A1

公开(公告)日：2024-02-22

申请号：US17888529

申请日：2022-08-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Hung Lin

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/5383 ,  H01L23/562 ,  H01L23/5385 ,  H01L23/49894 ,  H01L21/4857 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L24/13 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32221 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L24/29

摘要： A semiconductor package includes a package substrate a package substrate including: a substrate core; an upper redistribution layer disposed on a first side of the substrate core; and a lower redistribution layer disposed on an opposing second side of the substrate core; a semiconductor device vertically stacked on and electrically connected to the package substrate; and an upper reinforcement layer embedded in the upper redistribution layer between the semiconductor device and the substrate core, the upper reinforcement layer having a Young's modulus that is higher than a Young's modulus of the upper redistribution layer.

公开(公告)号：US10134717B2

公开(公告)日：2018-11-20

申请号：US15373719

申请日：2016-12-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Fan Huang ,  Tsai-Tsung Tsai ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

摘要： According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.