- 专利标题： SEMICONDUCTOR DIE INCLUDING STRESS-RESISTANT BONDING STRUCTURES AND METHODS OF FORMING THE SAME
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申请号： US18530286申请日： 2023-12-06
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公开(公告)号： US20240128219A1公开(公告)日： 2024-04-18
- 发明人: Hui-Min Huang , Wei-Hung Lin , Kai Jun Zhan , Chang-Jung Hsueh , Wan-Yu Chiang , Ming-Da Cheng
- 申请人： Taiwan Semiconductor Manufacturing Company Limited
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Company Limited
- 当前专利权人： Taiwan Semiconductor Manufacturing Company Limited
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L23/00
- IPC分类号： H01L23/00 ; H01L23/522
摘要：
A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
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