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1.发明授权公开(公告)号：US09530762B2
公开(公告)日：2016-12-27
申请号：US14152168
申请日：2014-01-10
发明人： Chen-Hua Yu , Chung-Shi Liu , Chih-Fan Huang , Tsai-Tsung Tsai , Wei-Hung Lin , Ming-Da Cheng
CPC分类号： H01L25/18 , H01L21/561 , H01L23/3114 , H01L23/3128 , H01L24/19 , H01L25/50 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/12042 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2224/48091
摘要： According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
摘要翻译： 根据示例性实施例，提供半导体封装。 A半导体封装包括至少一个芯片以及与至少一个芯片相邻的至少一个部件，其中所述至少一个芯片和所述至少一个部件被模制在相同的模制体中。
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2.发明公开公开(公告)号：US20240290703A1
公开(公告)日：2024-08-29
申请号：US18658006
申请日：2024-05-08
发明人： Kuo-Lung Pan , Yu-Chia Lai , Teng-Yuan Lo , Mao-Yen Chang , Po-Yuan Teng , Chen-Hua YU , Chung-Shi Liu , Hao-Yi Tsai , Tin-Hao Kuo
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L25/16 , H01L25/50
摘要： A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
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公开(公告)号：US10134717B2
公开(公告)日：2018-11-20
申请号：US15373719
申请日：2016-12-09
发明人： Chen-Hua Yu , Chung-Shi Liu , Chih-Fan Huang , Tsai-Tsung Tsai , Wei-Hung Lin , Ming-Da Cheng
摘要： According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
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公开(公告)号：US09425157B2
公开(公告)日：2016-08-23
申请号：US14190360
申请日：2014-02-26
发明人： Wei-Hung Lin , Hsiu-Jen Lin , Ming-Da Cheng , Yu-Min Liang , Chen-Shien Chen , Chung-Shi Liu
CPC分类号： H01L24/17 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/13005 , H01L2224/13082 , H01L2224/131 , H01L2224/1403 , H01L2224/16013 , H01L2224/16104 , H01L2224/16238 , H01L2224/1701 , H01L2224/1703 , H01L2224/17104 , H01L2924/014 , H01L2924/00014 , H01L2924/207
摘要： According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
摘要翻译： 根据示例性实施例，提供具有第一区域和第二区域的基板。 基板包括多个焊盘。 每个垫具有垫尺寸。 第一区域中的焊盘尺寸大于第二区域中的焊盘尺寸。
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5.发明授权公开(公告)号：US12014976B2
公开(公告)日：2024-06-18
申请号：US18191147
申请日：2023-03-28
发明人： Kuo Lung Pan , Yu-Chia Lai , Teng-Yuan Lo , Mao-Yen Chang , Po-Yuan Teng , Chen-Hua Yu , Chung-Shi Liu , Hao-Yi Tsai , Tin-Hao Kuo
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/00 , H01L25/16
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L25/16 , H01L25/50
摘要： A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
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6.发明授权公开(公告)号：US11646255B2
公开(公告)日：2023-05-09
申请号：US17205621
申请日：2021-03-18
发明人： Kuo Lung Pan , Yu-Chia Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu , Chen-Hua Yu , Po-Yuan Teng , Teng-Yuan Lo , Mao-Yen Chang
IPC分类号： H01L23/495 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/00 , H01L25/16 , H01L25/00
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L25/16 , H01L25/50
摘要： A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
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7.发明公开公开(公告)号：US20230253300A1
公开(公告)日：2023-08-10
申请号：US18191147
申请日：2023-03-28
发明人： Kuo Lung Pan , Yu-Chia Lai , Teng-Yuan Lo , Mao-Yen Chang , Po-Yuan Teng , Chen-Hua YU , Chung-Shi Liu , Hao-Yi Tsai , Ting-Hao Kuo
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L25/16 , H01L25/50
摘要： A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
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