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公开(公告)号:US20240290703A1
公开(公告)日:2024-08-29
申请号:US18658006
申请日:2024-05-08
发明人: Kuo-Lung Pan , Yu-Chia Lai , Teng-Yuan Lo , Mao-Yen Chang , Po-Yuan Teng , Chen-Hua YU , Chung-Shi Liu , Hao-Yi Tsai , Tin-Hao Kuo
CPC分类号: H01L23/49822 , H01L21/4857 , H01L23/3121 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L25/16 , H01L25/50
摘要: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.