专利检索 ap:("Taiwan Semiconductor Manufacturing Company, Ltd.") AND inv:"Yu-Nu Hsu" 第 1 页

1.

发明申请
Conductive External Connector Structure and Method of Forming 审中-公开

公开(公告)号：US20190131263A1

公开(公告)日：2019-05-02

申请号：US16226173

申请日：2018-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Fu Shih , Chun-Yen Lo , Cheng-Lin Huang , Wen-Ming Chen , Chien-Ming Huang , Yuan-Fu Liu , Yung-Chiuan Cheng , Wei-Chih Huang , Chen-Hsun Liu , Chien-Pin Chan , Yu-Nu Hsu , Chi-Hung Lin , Te-Hsun Pang , Chin-Yu Ku

IPC分类号： H01L23/00 , C25D5/50 , C25D17/12 , C25D21/10 , C25D5/12 , C25D17/00 , C25D7/12

摘要： External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

2.

发明授权
Conductive external connector structure and method of forming 有权

公开(公告)号：US10163836B2

公开(公告)日：2018-12-25

申请号：US15877186

申请日：2018-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Fu Shih , Chun-Yen Lo , Cheng-Lin Huang , Wen-Ming Chen , Chien-Ming Huang , Yuan-Fu Liu , Yung-Chiuan Cheng , Wei-Chih Huang , Chen-Hsun Liu , Chien-Pin Chan , Yu-Nu Hsu , Chi-Hung Lin , Te-Hsun Pang , Chin-Yu Ku

IPC分类号： H01L23/00 , C25D17/00 , H01L23/31

摘要： External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

3.

发明申请
Conductive External Connector Structure and Method of Forming 审中-公开

公开(公告)号：US20180166409A1

公开(公告)日：2018-06-14

申请号：US15877186

申请日：2018-01-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Fu Shih , Chun-Yen Lo , Cheng-Lin Huang , Wen-Ming Chen , Chien-Ming Huang , Yuan-Fu Liu , Yung-Chiuan Cheng , Wei-Chih Huang , Chen-Hsun Liu , Chien-Pin Chan , Yu-Nu Hsu , Chi-Hung Lin , Te-Hsun Pang , Chin-Yu Ku

IPC分类号： H01L23/00 , C25D17/00 , H01L23/31

CPC分类号： H01L24/11 , C25D17/001 , H01L23/3192 , H01L24/13 , H01L24/742 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05582 , H01L2224/05647 , H01L2224/1111 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13017 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13551 , H01L2224/13566 , H01L2224/1357 , H01L2224/13611 , H01L2924/01047 , H01L2924/00014 , H01L2924/014 , H01L2924/01074

摘要： External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

4.

发明授权
Conductive external connector structure and method of forming 有权

公开(公告)号：US10741513B2

公开(公告)日：2020-08-11

申请号：US16226173

申请日：2018-12-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Fu Shih , Chun-Yen Lo , Cheng-Lin Huang , Wen-Ming Chen , Chien-Ming Huang , Yuan-Fu Liu , Yung-Chiuan Cheng , Wei-Chih Huang , Chen-Hsun Liu , Chien-Pin Chan , Yu-Nu Hsu , Chi-Hung Lin , Te-Hsun Pang , Chin-Yu Ku

IPC分类号： H01L23/00 , C25D5/50 , C25D17/12 , C25D5/12 , C25D17/00 , C25D7/12 , C25D21/10 , H01L23/31 , C25D3/12 , C25D3/38 , C25D3/60

摘要： External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

5.

发明授权
Package structure with a barrier layer 有权

公开(公告)号：US11984419B2

公开(公告)日：2024-05-14

申请号：US17874021

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hung Chen , Yu-Nu Hsu , Chun-Chen Liu , Heng-Chi Huang , Chien-Chen Li , Shih-Yen Chen , Cheng-Nan Hsieh , Kuo-Chio Liu , Chen-Shien Chen , Chin-Yu Ku , Te-Hsun Pang , Yuan-Feng Wu , Sen-Chi Chiang

IPC分类号： H01L23/00 , H01L21/60 , H01L23/498

CPC分类号： H01L24/13 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0362 , H01L2224/03622 , H01L2224/0401 , H01L2224/10145 , H01L2224/1145 , H01L2224/11462 , H01L2224/1147 , H01L2224/11614 , H01L2224/11831 , H01L2224/11849 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13018 , H01L2224/13083 , H01L2224/13084 , H01L2224/13147 , H01L2224/13155 , H01L2224/16165 , H01L2224/16227 , H01L2224/16503 , H01L2224/16507 , H01L2224/73204 , H01L2224/81193 , H01L2224/8181 , H01L2224/81815 , H01L2924/01327 , H01L2924/2064 , H01L2224/11849 , H01L2924/00014 , H01L2224/13014 , H01L2924/00012 , H01L2224/13013 , H01L2924/00012 , H01L2224/13012 , H01L2924/00012 , H01L2224/11462 , H01L2924/00014 , H01L2224/1145 , H01L2924/00014 , H01L2224/81815 , H01L2924/00014

摘要： Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.

6.

发明授权
Method for forming package structure with a barrier layer 有权

公开(公告)号：US11469203B2

公开(公告)日：2022-10-11

申请号：US17072798

申请日：2020-10-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hung Chen , Yu-Nu Hsu , Chun-Chen Liu , Heng-Chi Huang , Chien-Chen Li , Shih-Yen Chen , Cheng-Nan Hsieh , Kuo-Chio Liu , Chen-Shien Chen , Chin-Yu Ku , Te-Hsun Pang , Yuan-Feng Wu , Sen-Chi Chiang

IPC分类号： H01L23/00 , H01L23/498

摘要： A method for forming a package structure includes forming an under bump metallization (UBM) layer over a metal pad and forming a photoresist layer over the UBM layer. The method further includes patterning the photoresist layer to form an opening in the photoresist layer. The method also includes forming a first bump structure over the first portion of the UBM layer. The first bump structure includes a first barrier layer over a first pillar layer. The method includes placing a second bump structure over the first bump structure. The second bump structure includes a second barrier layer over a second pillar layer. The method further includes reflowing the first bump structure and the second bump structure to form a solder joint between a first inter intermetallic compound (IMC) and a second IMC.

7.

发明授权
Semiconductor device 有权

公开(公告)号：US12021050B2

公开(公告)日：2024-06-25

申请号：US17814840

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-Ho Tsai , Jyun-Hong Chen , Chun-Chen Liu , Yu-Nu Hsu , Peng-Ren Chen , Wen-Hao Cheng , Chi-Ming Tsai

IPC分类号： H01L23/00

CPC分类号： H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/11462 , H01L2224/11618 , H01L2224/117 , H01L2224/11849 , H01L2224/13026 , H01L2224/13147 , H01L2224/1403

摘要： A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

8.

发明授权
Semiconductor device manufacturing method and associated semiconductor die 有权

公开(公告)号：US11469198B2

公开(公告)日：2022-10-11

申请号：US16353425

申请日：2019-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ming-Ho Tsai , Jyun-Hong Chen , Chun-Chen Liu , Yu-Nu Hsu , Peng-Ren Chen , Wen-Hao Cheng , Chi-Ming Tsai

IPC分类号： H01L23/48 , H01L23/00

摘要： A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.