公开(公告)号：US20170221845A1

公开(公告)日：2017-08-03

申请号：US15490716

申请日：2017-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/09 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0214 ,  H01L2224/02175 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0381 ,  H01L2224/0382 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06179 ,  H01L2224/0912 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/00012

摘要： Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

公开(公告)号：US09698079B2

公开(公告)日：2017-07-04

申请号：US14147338

申请日：2014-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Chun Miao ,  Shih-Wei Liang ,  Kai-Chiang Wu

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02245 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/11013 ,  H01L2224/11916 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2924/00011 ,  H01L2924/013 ,  H01L2924/01322 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/81805

摘要： A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

公开(公告)号：US20170170161A1

公开(公告)日：2017-06-15

申请号：US15443827

申请日：2017-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC分类号： H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/1134 ,  H01L2224/1148 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014

摘要： An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US20170033079A1

公开(公告)日：2017-02-02

申请号：US15184657

申请日：2016-06-16

申请人： MediaTek Inc.

发明人： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC分类号： H01L25/065 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

摘要： A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.

摘要翻译： 提供半导体封装结构。 半导体封装结构包括在基板上的第一电子部件。 半导体封装结构还包括堆叠在第一电子部件上的第二电子部件。 第一电子部件的有源表面面向第二电子部件的有效表面。 半导体封装结构还包括在第一电子元件上并包围第二电子元件的模塑料。 此外，半导体封装结构包括堆叠在第二电子部件和模塑料上的第三电子部件。

公开(公告)号：US09508668B2

公开(公告)日：2016-11-29

申请号：US14804617

申请日：2015-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

摘要翻译： 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸起结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下金属（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱的前端具有柱宽，UBM宽度大于柱宽。

公开(公告)号：US09508594B2

公开(公告)日：2016-11-29

申请号：US14930984

申请日：2015-11-03

申请人： International Business Machines Corporation

发明人： Toyohiro Aoki ,  Hiroyuki Mori ,  Kazushige Toriyama

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  B23K3/06 ,  H01L23/488 ,  H01L23/48

CPC分类号： H01L24/13 ,  B23K3/0623 ,  H01L21/4867 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/34 ,  H01L23/345 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/11013 ,  H01L2224/1131 ,  H01L2224/11312 ,  H01L2224/11416 ,  H01L2224/1148 ,  H01L2224/11618 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17519 ,  H01L2224/27 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/12042 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00013 ,  H01L2924/00012

摘要： A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.

公开(公告)号：US09397056B2

公开(公告)日：2016-07-19

申请号：US14294531

申请日：2014-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yen-Ping Wang ,  Chao-Wen Shih ,  Yung-Ping Chiang ,  Shih-Wei Liang ,  Tsung-Yuan Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L23/525

CPC分类号： H01L24/05 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/538 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/11013 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： In some embodiments in accordance with the present disclosure, a semiconductor device including a semiconductor substrate is received. An interconnect structure is provided over the semiconductor substrate, and a passivation is provided over the interconnect structure. The passivation includes an opening such that a portion of the interconnect structure is exposed. Moreover, a dielectric is provided over the passivation, and a post-passivation interconnect (PPI) is provided over the dielectric. The PPI is configured to connect with the exposed portion of the interconnect structure through an opening in the dielectric. Furthermore, the PPI includes a receiving area for receiving a conductor, and a trench adjacent to the receiving area. In certain embodiments, the receiving area is defined by the trench.

摘要翻译： 在根据本公开的一些实施例中，接收包括半导体衬底的半导体器件。 在半导体衬底上提供互连结构，并且在互连结构上提供钝化。 钝化包括使得互连结构的一部分露出的开口。 此外，在钝化上提供电介质，并且在电介质上提供钝化后互连（PPI）。 PPI被配置为通过电介质中的开口与互连结构的暴露部分连接。 此外，PPI包括用于接收导体的接收区域和与接收区域相邻的沟槽。 在某些实施例中，接收区域由沟槽限定。

公开(公告)号：US09379077B2

公开(公告)日：2016-06-28

申请号：US14440876

申请日：2013-10-30

申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD.

发明人： Chang-Ming Lin ,  Lei Shi ,  Honghui Wang

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/78 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11902 ,  H01L2224/11903 ,  H01L2224/13007 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/45147 ,  H01L2224/78303 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable.

摘要翻译： 一种半导体器件封装和封装方法，所述半导体器件封装方法包括：为芯片提供形成在所述芯片表面上的焊盘; 在所述芯片表面上形成钝化层和凸块，其中所述钝化层具有暴露所述焊盘部分的开口，所述凸块位于所述开口中，并且所述凸块的尺寸小于所述开口的尺寸; 形成覆盖凸起的顶表面和侧壁以及开口的底表面的焊球。 形成的半导体器件封装不容易形成短路。 焊球与凸块之间的接合强度高，半导体器件的性能稳定。

公开(公告)号：US20160056119A1

公开(公告)日：2016-02-25

申请号：US14678674

申请日：2015-04-03

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Seok-Yoon HONG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2021/60022 ,  H01L2224/11013 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

摘要： A flip chip package and a manufacturing method thereof are disclosed. The flip chip package in accordance with an embodiment of the present invention includes: a substrate; a plurality of pads formed on the substrate; a solder resist covering the substrate in such a way that the pads are exposed; a chip mounted on the substrate in such a way that the chip is electrically connected with the pads; a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip; and an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps.

公开(公告)号：US20150348925A1

公开(公告)日：2015-12-03

申请号：US14725242

申请日：2015-05-29

申请人： APPLIED Materials, Inc.

发明人： David P. Surdock ,  Marvin L. Bernt

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  C23F1/26 ,  C23F1/38 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/11005 ,  H01L2224/11013 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/1357 ,  H01L2224/13666 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2224/0231 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/00012

摘要： In accordance with one embodiment of the present disclosure, a method of forming a metal feature includes etching a portion of a first metal layer using a first etching chemistry, and etching a portion of a barrier layer using a second etching chemistry to achieve a barrier layer undercut of less than or equal to 2 times the thickness of the barrier layer.

摘要翻译： 根据本公开的一个实施例，形成金属特征的方法包括使用第一蚀刻化学法蚀刻第一金属层的一部分，并且使用第二蚀刻化学法蚀刻阻挡层的一部分以实现阻挡层 底切小于或等于阻挡层厚度的2倍。