公开(公告)号：US20160276324A1

公开(公告)日：2016-09-22

申请号：US15014636

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/522 ,  H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括包括第一半导体管芯的第一半导体封装。 第一再分配层（RDL）结构耦合到第一半导体管芯。 第一再分配层（RDL）结构包括设置在第一层级的第一导电迹线。 第二导电迹线设置在第二层级。 位于第一导电迹线和第二导电迹线之间的第一金属间电介质（IMD）层之外的第一金属间介电层（IMD）层和第二金属间介电层（IMD）层。

公开(公告)号：US20170373038A1

公开(公告)日：2017-12-28

申请号：US15696247

申请日：2017-09-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L25/16 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.

公开(公告)号：US20170098629A1

公开(公告)日：2017-04-06

申请号：US15218379

申请日：2016-07-25

Applicant: MediaTek Inc.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/83

Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

公开(公告)号：US20170098589A1

公开(公告)日：2017-04-06

申请号：US15212113

申请日：2016-07-15

Applicant: MediaTek Inc.

Inventor： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/29016 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001

Abstract: A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.

公开(公告)号：US20160268234A1

公开(公告)日：2016-09-15

申请号：US15014604

申请日：2016-02-03

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括半导体管芯。 第一模塑料覆盖半导体管芯的背面。 再分布层（RDL）结构设置在半导体管芯的前表面上。 半导体管芯耦合到RDL结构。 第二模塑料被设置在半导体管芯的前表面并嵌入RDL结构中。 无源器件设置在第二模塑料上并与半导体管芯耦合。

公开(公告)号：US20170287877A1

公开(公告)日：2017-10-05

申请号：US15624790

申请日：2017-06-16

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.

公开(公告)号：US20170278832A1

公开(公告)日：2017-09-28

申请号：US15618210

申请日：2017-06-09

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/16 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.

公开(公告)号：US20160343694A1

公开(公告)日：2016-11-24

申请号：US15066241

申请日：2016-03-10

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO

IPC: H01L25/16 ,  H01L21/78 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

Abstract translation: 提供半导体封装组件。 半导体封装组件包括半导体封装。 半导体封装包括半导体管芯。 再分配层（RDL）结构设置在半导体管芯上并与半导体管芯电连接。 有源或无源元件设置在半导体管芯和RDL结构之间。 模制化合物围绕半导体管芯和有源或无源元件。

公开(公告)号：US20170243826A1

公开(公告)日：2017-08-24

申请号：US15418896

申请日：2017-01-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Nai-Wei LIU ,  Wei-Che HUANG

IPC: H01L23/538 ,  H01L49/02 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

公开(公告)号：US20170033079A1

公开(公告)日：2017-02-02

申请号：US15184657

申请日：2016-06-16

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC: H01L25/065 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.

Abstract translation: 提供半导体封装结构。 半导体封装结构包括在基板上的第一电子部件。 半导体封装结构还包括堆叠在第一电子部件上的第二电子部件。 第一电子部件的有源表面面向第二电子部件的有效表面。 半导体封装结构还包括在第一电子元件上并包围第二电子元件的模塑料。 此外，半导体封装结构包括堆叠在第二电子部件和模塑料上的第三电子部件。