公开(公告)号：US20180226372A1

公开(公告)日：2018-08-09

申请号：US15428130

申请日：2017-02-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po-Chun LIN

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1162 ,  H01L2224/11622 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/81047 ,  H01L2224/812 ,  H01L2225/06513 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/20106 ,  H01L2924/01007

摘要： A package structure includes a semiconductor substrate, an under bump metallurgy layer, and at least one bump. The under bump metallurgy layer is disposed on the semiconductor substrate. The bump is disposed on the under bump metallurgy layer, and the bump includes a first portion and a second portion under the first portion, wherein a top surface of the first portion of the bump includes a flat portion and a rounded portion.

公开(公告)号：US10037967B1

公开(公告)日：2018-07-31

申请号：US15454229

申请日：2017-03-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Toyohiro Aoki ,  Takashi Hisada ,  Eiji Nakamura ,  Kuniaki Sueoka

IPC分类号： H01L23/00 ,  H01L21/56 ,  B23K3/06 ,  B23K1/00 ,  B23K35/02

CPC分类号： H01L24/81 ,  B23K1/0016 ,  B23K3/0623 ,  B23K3/0638 ,  B23K35/0238 ,  B23K35/0244 ,  H01L21/565 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05683 ,  H01L2224/05684 ,  H01L2224/11312 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2224/11 ,  H01L2224/03

摘要： Methods for depositing material on a chip include forming a mold layer on a substrate. The mold layer has one or more openings over respective contact areas on the substrate. The one or more openings are formed from an upper volume and a lower volume, the upper volume having a smaller diameter than a diameter of the lower volume. A material is injected into the one or more openings under pressure, such that gas trapped in the one or more openings displaces into the lower volume until the injected material in the one or more openings makes contact with each respective contact area.

公开(公告)号：US20170309596A1

公开(公告)日：2017-10-26

申请号：US15645487

申请日：2017-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh ,  Kuo-Chung Yee ,  Jui-Pin Hung

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/321 ,  H01L21/288 ,  H01L21/027

CPC分类号： H01L25/0652 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11616 ,  H01L2224/11622 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/82 ,  H01L2924/00012

摘要： A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

公开(公告)号：US09553064B2

公开(公告)日：2017-01-24

申请号：US15054413

申请日：2016-02-26

申请人： SEIKO EPSON CORPORATION

发明人： Yoshihide Matsuo ,  Masashi Yoshiike

IPC分类号： B41J2/14 ,  H01L23/00

CPC分类号： H01L24/13 ,  B41J2/14233 ,  B41J2/161 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2002/14241 ,  B41J2002/14491 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05655 ,  H01L2224/1161 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/13008 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16227 ,  H01L2224/27618 ,  H01L2224/27622 ,  H01L2224/27901 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/29024 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/301 ,  H01L2224/30145 ,  H01L2224/32237 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81444 ,  H01L2224/81903 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83455 ,  H01L2224/83466 ,  H01L2224/83471 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/0635 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/0615 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2224/27848 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83

摘要： An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

摘要翻译： 电子装置包括：压电元件的驱动基板（压力室基板和振动板），与形成在其上的压电元件的驱动有关的电极布线;以及密封板，电极布线由布线金属 金（Au）通过作为基底层的粘合层在驱动基板上，并且具有去除部分，其中在包含粘合到接合树脂的部分的区域中的布线金属的一部分被去除并且粘附层暴露 。

公开(公告)号：US09418955B2

公开(公告)日：2016-08-16

申请号：US14096435

申请日：2013-12-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  H05K3/40

CPC分类号： H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

摘要： A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

摘要翻译： 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US09324671B2

公开(公告)日：2016-04-26

申请号：US14660376

申请日：2015-03-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Guowei Zhang

IPC分类号： H01L21/44 ,  H01L29/40 ,  H01L23/00

CPC分类号： H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11622 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/9212 ,  H01L2924/05042 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/034 ,  H01L2224/1147 ,  H01L2224/114

摘要： A method for fabrication a metal pillar bump packaging structure is provided. The method includes providing a semiconductor substrate; and forming a metal interconnect structure and a dielectric layer exposing a portion of the metal interconnect structure on the semiconductor substrate. The method also includes forming a photoresist layer having an opening with an undercut with a bottom area greater than a top area at the bottom of the opening to expose the metal interconnect structure and a portion of the dielectric layer on the semiconductor substrate; and forming a metal pillar bump structure having a pillar body and an extension part with an enlarged bottom area in the opening and the undercut. Further, the method includes forming a soldering ball on the metal pillar bump structure.

摘要翻译： 提供一种用于制造金属柱凸块包装结构的方法。 该方法包括：提供半导体衬底; 以及形成金属互连结构和暴露所述半导体衬底上的所述金属互连结构的一部分的电介质层。 该方法还包括形成具有底切的开口的光刻胶层，底部区域大于开口底部的顶部区域，以露出金属互连结构和半导体衬底上的介电层的一部分; 以及形成具有柱体和延伸部的金属柱状凸起结构，该开口和底切具有扩大的底部区域。 此外，该方法包括在金属柱状凸起结构上形成焊球。

公开(公告)号：US09324557B2

公开(公告)日：2016-04-26

申请号：US14259530

申请日：2014-04-23

申请人： LSI Corporation

发明人： Steven D. Cate ,  John W. Osenbach

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L21/00 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/81447 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/37 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/206 ,  H01L2224/03

摘要： A process to form metal pillars on a flip-chip device. The pillars, along with a layer of solder, will be used to bond die pads on the device to respective substrate pads on a substrate. A photoresist is deposited over the device and a first set of die pads on the device are exposed by forming openings of a first diameter in the photoresist. Pillars of the first diameter are formed by electroplating metal onto the exposed die pads. Then a second photoresist deposited over the first photoresist covers the pillars of the first diameter. Openings of a second diameter are formed in the first and second photoresists to expose a second set of die pads. Pillars of the second diameter are formed by electroplating metal onto the exposed die pads. The photoresists are then removed along with conductive layers on the device used as part of the plating process.

摘要翻译： 一种在倒装芯片上形成金属柱的工艺。 支柱以及一层焊料将用于将器件上的管芯焊盘与衬底上相应的衬底焊盘接合。 在器件上沉积光致抗蚀剂，并且通过在光致抗蚀剂中形成第一直径的开口来暴露器件上的第一组裸片焊盘。 通过将金属电镀到暴露的裸片上而形成第一直径的支柱。 然后沉积在第一光致抗蚀剂上的第二光致抗蚀剂覆盖第一直径的柱。 在第一和第二光致抗蚀剂中形成第二直径的开口以暴露第二组裸片。 通过将金属电镀在暴露的裸片上形成第二直径的支柱。 然后将光致抗蚀剂与用作电镀工艺的一部分的器件上的导电层一起除去。

公开(公告)号：US20160079193A1

公开(公告)日：2016-03-17

申请号：US14484313

申请日：2014-09-12

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Brian M. Erwin ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05023 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0544 ,  H01L2924/3841 ,  H01L2924/00014

摘要： A method including forming a copper pillar, electroplating a metal layer on a top surface and a sidewall of the copper pillar, and electroplating a metal cap above the top surface of the copper pillar in direct contact with the metal layer. The method further including forming an intermetallic by heating the metal layer and the copper pillar in a non-reducing environment, the intermetallic including elements of both the copper pillar and the metal layer, where molten solder will wet to the metal cap and will not wet to the intermetallic.

摘要翻译： 一种包括形成铜柱的方法，在铜柱的顶表面和侧壁上电镀金属层，并且在铜柱的顶表面上方与金属层直接接触地电镀金属帽。 该方法还包括通过在非还原环境中加热金属层和铜柱形成金属间化合物，金属间化合物包括铜柱和金属层的元素，其中熔融的焊料将润湿金属帽并且不会湿润 到金属间化合物。

公开(公告)号：US20150262920A1

公开(公告)日：2015-09-17

申请号：US14215605

申请日：2014-03-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： You Chye How ,  Huay Yann Tay

IPC分类号： H01L23/495 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L24/13 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02205 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

摘要： An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces.

摘要翻译： 一种集成电路（“IC”）封装，其包括至少一个具有第一侧的IC管芯，其上具有至少两个相邻的凸点焊盘和与第一侧相对的第二侧; 第一基板，其上具有多个电接触表面的第一侧; 以及多个铜柱，每个铜柱具有附接到相邻凸块之一的第一端和连接到电接触表面之一的第二端。

公开(公告)号：US09117697B2

公开(公告)日：2015-08-25

申请号：US14303371

申请日：2014-06-12

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chun-Che Lee ,  Yuan-Chang Su ,  Wen-Chi Cheng ,  Guo-Cheng Liao ,  Yi-Chuan Ding

IPC分类号： H01L23/52 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

摘要： The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

摘要翻译： 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。