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公开(公告)号:US20120025365A1
公开(公告)日:2012-02-02
申请号:US12844463
申请日:2010-07-27
申请人: Belgacem Haba
发明人: Belgacem Haba
CPC分类号: H01L24/17 , B82Y40/00 , H01L21/4853 , H01L21/50 , H01L23/49811 , H01L23/52 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05644 , H01L2224/05647 , H01L2224/06181 , H01L2224/116 , H01L2224/1182 , H01L2224/11821 , H01L2224/13101 , H01L2224/13144 , H01L2224/13147 , H01L2224/13644 , H01L2224/13794 , H01L2224/13911 , H01L2224/13944 , H01L2224/13947 , H01L2224/16057 , H01L2224/16113 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/29111 , H01L2224/73104 , H01L2224/81026 , H01L2224/81099 , H01L2224/81143 , H01L2224/81192 , H01L2224/81193 , H01L2224/81444 , H01L2224/81447 , H01L2224/81801 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15321 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , Y10S977/773 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要: A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.
摘要翻译: 制造组件的方法包括以下步骤:将金属纳米颗粒施加到第一部件和第二部件中的任一个或两者的导电元件的暴露表面上,将第一部件的导电元件与第二部件的导电元件并置, 设置在其间的金属纳米颗粒,并且至少在并置的导电元件的界面处将温度升高到金属纳米粒子在并置的导电元件之间形成冶金接头的接合温度。 第一部件和第二部件中的任一个或两者的导电元件可以包括基本上刚性的支柱,其具有突出在相应部件的表面上方的高度的顶表面,并且远离其顶表面以基本角度延伸的边缘表面。
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公开(公告)号:US07618844B2
公开(公告)日:2009-11-17
申请号:US11206605
申请日:2005-08-18
申请人: James Sheats
发明人: James Sheats
CPC分类号: H01L25/0655 , H01L21/4867 , H01L23/4985 , H01L23/49866 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/90 , H01L2224/0401 , H01L2224/05571 , H01L2224/05705 , H01L2224/05794 , H01L2224/058 , H01L2224/05811 , H01L2224/0582 , H01L2224/05824 , H01L2224/05839 , H01L2224/05844 , H01L2224/05847 , H01L2224/05849 , H01L2224/05855 , H01L2224/05857 , H01L2224/0586 , H01L2224/05866 , H01L2224/05869 , H01L2224/05871 , H01L2224/05872 , H01L2224/0588 , H01L2224/05884 , H01L2224/1132 , H01L2224/114 , H01L2224/116 , H01L2224/13099 , H01L2224/16237 , H01L2224/81097 , H01L2224/81099 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2224/90 , H01L2924/0001 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1532 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K3/3452 , H05K3/3463 , H01L2924/0108 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要: A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.
摘要翻译: 公开了一种在柔性基板上的半导体芯片封装。 芯片和柔性基板设置有对应的凸起和凹入的微米级接触垫,其中凹入的接触垫部分地填充有液体汞齐。 低温汞合金固化后,芯片和基板形成柔性基板IC封装,导电性高,界面层厚度可控,微米级接触密度低,工艺温度低。 通过用非导电粘合剂涂覆其它区域,可以进一步提高芯片和基板之间的粘合性。
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公开(公告)号:US20180218998A1
公开(公告)日:2018-08-02
申请号:US15937149
申请日:2018-03-27
申请人: Invensas Corporation
发明人: Cyprian Emeka Uzoh
IPC分类号: H01L23/00 , H01L25/065 , H01L25/00
CPC分类号: H01L24/81 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/80 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2224/03009 , H01L2224/0401 , H01L2224/05571 , H01L2224/05572 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05639 , H01L2224/05644 , H01L2224/05684 , H01L2224/11009 , H01L2224/11464 , H01L2224/13018 , H01L2224/13019 , H01L2224/13084 , H01L2224/13562 , H01L2224/13564 , H01L2224/13655 , H01L2224/13684 , H01L2224/13686 , H01L2224/13805 , H01L2224/13809 , H01L2224/13811 , H01L2224/13844 , H01L2224/13847 , H01L2224/13855 , H01L2224/16148 , H01L2224/16238 , H01L2224/16265 , H01L2224/16268 , H01L2224/16501 , H01L2224/2919 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81026 , H01L2224/81065 , H01L2224/81099 , H01L2224/81193 , H01L2224/8181 , H01L2224/83026 , H01L2224/83815 , H01L2225/06513 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/19043 , H01L2924/19104 , H01L2924/3841 , H01L2924/013 , H01L2924/00014 , H01L2924/00012
摘要: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
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公开(公告)号:US10002842B2
公开(公告)日:2018-06-19
申请号:US15132711
申请日:2016-04-19
发明人: François Marion
IPC分类号: H01L23/00 , H01L25/065 , H01L25/00 , H05K3/10
CPC分类号: H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/114 , H01L2224/11452 , H01L2224/1147 , H01L2224/116 , H01L2224/1161 , H01L2224/11614 , H01L2224/11827 , H01L2224/11901 , H01L2224/13011 , H01L2224/13019 , H01L2224/13023 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13172 , H01L2224/1318 , H01L2224/13184 , H01L2224/13566 , H01L2224/13582 , H01L2224/13624 , H01L2224/13687 , H01L2224/16145 , H01L2224/81099 , H01L2224/81193 , H01L2224/81208 , H01L2224/81355 , H01L2224/81801 , H01L2225/06513 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H05K3/10 , Y10T29/49117 , H01L2924/00014 , H01L2224/131
摘要: A method of producing a hybridized device including two microelectronic components, including a first microelectronic component having conductive inserts on a connection surface, and a second microelectronic component having ductile conductive pads on a surface opposed to the connection surface, is provided. The method includes the steps of hybridizing the first and second electronic components face-to-face by arranging the connection surface of the first microelectronic component to oppose the surface of the second microelectronic component having the ductile conductive pads, and establishing an electro-mechanical connection between the first microelectronic component and the second microelectronic component by inserting, at ambient temperature, inserts of the first microelectronic component, provided with a second metal sub-layer, into the ductile conductive pads of the second microelectronic component.
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公开(公告)号:US20180132399A1
公开(公告)日:2018-05-10
申请号:US15670127
申请日:2017-08-07
发明人: Eric Frank Schulte
CPC分类号: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
摘要: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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公开(公告)号:US20180132395A1
公开(公告)日:2018-05-10
申请号:US15670010
申请日:2017-08-07
发明人: Eric Frank Schulte
CPC分类号: H05K13/046 , B32B38/0008 , B32B2310/14 , B32B2457/00 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0381 , H01L2224/0401 , H01L2224/05552 , H01L2224/05557 , H01L2224/05568 , H01L2224/05655 , H01L2224/11334 , H01L2224/1181 , H01L2224/11831 , H01L2224/13099 , H01L2224/131 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/16145 , H01L2224/81011 , H01L2224/81013 , H01L2224/81054 , H01L2224/81099 , H01L2224/81191 , H01L2224/81193 , H01L2224/812 , H01L2224/81201 , H01L2224/81365 , H01L2224/81895 , H01L2224/81897 , H01L2225/06513 , H01L2225/06565 , H01L2924/00 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1431 , H01L2924/1461
摘要: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.
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公开(公告)号:US20170084570A1
公开(公告)日:2017-03-23
申请号:US15310684
申请日:2015-06-22
发明人: Sunil Wickramanayaka , Ling Xie , Jerry Jie Li Aw
IPC分类号: H01L23/00 , H01L25/065 , H01L25/00
CPC分类号: H01L24/81 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/0361 , H01L2224/03622 , H01L2224/0401 , H01L2224/05147 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11825 , H01L2224/1184 , H01L2224/11845 , H01L2224/119 , H01L2224/13023 , H01L2224/13026 , H01L2224/13147 , H01L2224/13562 , H01L2224/13611 , H01L2224/16225 , H01L2224/81022 , H01L2224/8109 , H01L2224/81097 , H01L2224/81099 , H01L2224/81192 , H01L2224/81193 , H01L2224/81203 , H01L2224/8181 , H01L2224/8182 , H01L2224/8183 , H01L2224/81986 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2924/3841 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/81 , H01L2224/9205
摘要: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.
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28.
公开(公告)号:US20170062273A1
公开(公告)日:2017-03-02
申请号:US15261343
申请日:2016-09-09
申请人: Huilong ZHU
发明人: Huilong ZHU
IPC分类号: H01L21/768 , H01L23/532 , H01L25/00 , H01L23/538 , H01L25/065
CPC分类号: H01L21/76883 , H01L21/76807 , H01L21/76832 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/53233 , H01L23/53238 , H01L23/53247 , H01L23/53261 , H01L23/5329 , H01L23/5382 , H01L23/5386 , H01L24/02 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/02335 , H01L2224/0401 , H01L2224/05006 , H01L2224/05026 , H01L2224/05546 , H01L2224/05554 , H01L2224/05571 , H01L2224/05647 , H01L2224/1146 , H01L2224/11472 , H01L2224/11616 , H01L2224/11903 , H01L2224/13017 , H01L2224/13018 , H01L2224/13024 , H01L2224/1308 , H01L2224/13083 , H01L2224/13099 , H01L2224/13147 , H01L2224/16145 , H01L2224/8012 , H01L2224/80895 , H01L2224/80896 , H01L2224/81097 , H01L2224/81099 , H01L2224/81208 , H01L2224/94 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2224/81
摘要: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close undesirable opens or voids between contacts of the two integrated circuits.
摘要翻译: 公开了通过Z字形导电链将3D布置中的至少两个集成电路连接起来的方法和结构。 在晶片接合工艺中用作弹簧或自适应接触结构(SACS)的之字形导电链被设计为减少键合界面应力,增加键合界面的可靠性,以及具有可调整的高度以闭合不期望的开口或空隙 在两个集成电路的触点之间。
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公开(公告)号:US08291586B2
公开(公告)日:2012-10-23
申请号:US12852726
申请日:2010-08-09
申请人: Francois Marion
发明人: Francois Marion
CPC分类号: H01L25/50 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/13005 , H01L2224/13011 , H01L2224/13014 , H01L2224/13015 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13186 , H01L2224/1357 , H01L2224/13644 , H01L2224/13669 , H01L2224/1601 , H01L2224/16105 , H01L2224/81099 , H01L2224/81193 , H01L2224/81194 , H01L2224/81201 , H01L2224/81898 , H01L2225/06513 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , Y10T29/49149 , Y10T29/49179 , Y10T29/49826 , H01L2924/01014 , H01L2924/04941 , H01L2924/00014 , H01L2924/01051 , H01L2924/207
摘要: A method for bonding two electronic components includes inserting hollow and open inserts into full convex elements of a lower hardness than that of the inserts, where, when an insert is inserted into a full element at least one surface of the open end of the insert is left free from the full element so as to create an outlet passage for gases contained in the insert.
摘要翻译: 一种用于接合两个电子部件的方法包括将中空的和开放的插入件插入比嵌入件的硬度更低的完整的凸形元件中,其中当插入件插入到完整的元件中时,插入件的开口端的至少一个表面是 离开整个元件,以便为包含在插入件中的气体形成出口通道。
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公开(公告)号:US20110035925A1
公开(公告)日:2011-02-17
申请号:US12852726
申请日:2010-08-09
申请人: Francois MARION
发明人: Francois MARION
IPC分类号: B23P19/04
CPC分类号: H01L25/50 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/13005 , H01L2224/13011 , H01L2224/13014 , H01L2224/13015 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/13186 , H01L2224/1357 , H01L2224/13644 , H01L2224/13669 , H01L2224/1601 , H01L2224/16105 , H01L2224/81099 , H01L2224/81193 , H01L2224/81194 , H01L2224/81201 , H01L2224/81898 , H01L2225/06513 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , Y10T29/49149 , Y10T29/49179 , Y10T29/49826 , H01L2924/01014 , H01L2924/04941 , H01L2924/00014 , H01L2924/01051 , H01L2924/207
摘要: This method for bonding two electronic components (12, 16) by the insertion of hollow and open inserts (50) into full convex elements (14) of lower hardness than that of the inserts, consists, when an insert (50) is inserted into a full element (14), in that at least one surface (52) of the open end (54) of the insert (50) is left free so as to create an outlet passage for gases contained in the insert (50).
摘要翻译: 通过将中空和开放的插入件(50)插入到比插入件的硬度更低的硬度的完全凸起元件(14)中来接合两个电子部件(12,16)的这种方法包括当插入件(50)被插入 完整元件(14),其中插入件(50)的开口端(54)的至少一个表面(52)是自由的,以便为包含在插入件(50)中的气体形成出口通道。
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