公开(公告)号：US09640519B2

公开(公告)日：2017-05-02

申请号：US14737072

申请日：2015-06-11

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC分类号： H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L29/06 ,  H01L23/498

CPC分类号： H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

摘要： A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20170103955A1

公开(公告)日：2017-04-13

申请号：US15385100

申请日：2016-12-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： YUNG-PING CHIANG ,  CHAO-WEN SHIH ,  HAO-YI TSAI ,  MIRNG-JI LII

IPC分类号： H01L23/00 ,  H01L21/66

CPC分类号： H01L24/02 ,  H01L21/31053 ,  H01L21/56 ,  H01L22/12 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11602 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/92 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11

摘要： A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.

公开(公告)号：US20170092609A1

公开(公告)日：2017-03-30

申请号：US15271405

申请日：2016-09-21

申请人： Renesas Electronics Corporation

发明人： Akira YAJIMA

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05664 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14517 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/01022 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2924/01073 ,  H01L2924/0496 ,  H01L2924/01046 ,  H01L2924/01044 ,  H01L2924/01078 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00

摘要： In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.

公开(公告)号：US09607914B2

公开(公告)日：2017-03-28

申请号：US14434239

申请日：2014-05-15

申请人： Intel Corporation

发明人： Paul J. Gwin

IPC分类号： H01L23/053 ,  H01L23/04 ,  H01L23/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/08 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/053 ,  G06F1/18 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4817 ,  H01L21/50 ,  H01L21/565 ,  H01L23/04 ,  H01L23/06 ,  H01L23/08 ,  H01L23/10 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/0615 ,  H01L2924/0635 ,  H01L2924/065 ,  H01L2924/068 ,  H01L2924/069 ,  H01L2924/0695 ,  H01L2924/0705 ,  H01L2924/10253 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15153 ,  H01L2924/16152 ,  H01L2924/16176 ,  H01L2924/1619 ,  H01L2924/19105 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.

公开(公告)号：US20170062273A1

公开(公告)日：2017-03-02

申请号：US15261343

申请日：2016-09-09

申请人： Huilong ZHU

发明人： Huilong ZHU

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L21/76883 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53261 ,  H01L23/5329 ,  H01L23/5382 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05026 ,  H01L2224/05546 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11616 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/8012 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81097 ,  H01L2224/81099 ,  H01L2224/81208 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81

摘要： Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close undesirable opens or voids between contacts of the two integrated circuits.

摘要翻译： 公开了通过Z字形导电链将3D布置中的至少两个集成电路连接起来的方法和结构。 在晶片接合工艺中用作弹簧或自适应接触结构（SACS）的之字形导电链被设计为减少键合界面应力，增加键合界面的可靠性，以及具有可调整的高度以闭合不期望的开口或空隙 在两个集成电路的触点之间。

公开(公告)号：US09570350B2

公开(公告)日：2017-02-14

申请号：US14789908

申请日：2015-07-01

申请人： Micron Technology, Inc.

发明人： Mark E. Tuttle

IPC分类号： H01L21/768 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L21/76898 ,  H01L21/76895 ,  H01L23/552 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599

摘要： Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.

摘要翻译： 具有互连和导电背板的微特征工件以及相关联的系统和方法在本文中公开。 一种这样的器件包括具有集成电路和电耦合到集成电路的端子的半导体衬底。 该器件还包括延伸穿过半导体衬底的至少一部分并电耦合到相应端子的导电互连。 该器件还包括导电底板组件，其在半导体衬底的背面具有导电层。 一个或多个互连件在半导体衬底的背面电耦合到导电层。

公开(公告)号：US20170040295A1

公开(公告)日：2017-02-09

申请号：US15299483

申请日：2016-10-21

申请人： Empire Technology Development LLC

发明人： Zhijiong Luo

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/187 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76889 ,  H01L21/8221 ,  H01L23/34 ,  H01L23/36 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/50 ,  H01L2021/60007 ,  H01L2021/60097 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27614 ,  H01L2224/27848 ,  H01L2224/29006 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32113 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/325 ,  H01L2224/32503 ,  H01L2224/7525 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/83048 ,  H01L2224/838 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83931 ,  H01L2224/83948 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0474 ,  H01L2924/0475 ,  H01L2924/0476 ,  H01L2924/048 ,  H01L2924/0481 ,  H01L2924/0483 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/056 ,  H01L2924/047 ,  H01L2924/00012

摘要： Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

摘要翻译： 通常将技术描述为具有用于散热间隔的集成电路（IC）的三维集成。 根据一些示例，自对准硅化物可以形成在临时硅层中，并且在晶片的结合之后被去除，以通过在IC之间增加的间隔来实现组合IC之间的改善的接触和增强的散热。

公开(公告)号：US20170012018A1

公开(公告)日：2017-01-12

申请号：US15276156

申请日：2016-09-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hirohiko WATANABE ,  Shunsuke SAITO ,  Masahiro ONO ,  Takashi WATANABE ,  Shinji SANO ,  Kazunaga ONISHI

IPC分类号： H01L23/00 ,  B23K35/26 ,  H01L21/52 ,  B23K1/00

CPC分类号： H01L24/48 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/19 ,  B23K1/203 ,  B23K35/26 ,  B23K35/262 ,  B23K2101/42 ,  C22C13/02 ,  H01L21/52 ,  H01L23/40 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/81 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05639 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/48506 ,  H01L2224/4852 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85359 ,  H01L2224/85805 ,  H01L2224/85825 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H05K3/3463 ,  H05K2201/10166 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01026 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/0103 ,  H01L2924/01078 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01051 ,  H01L2224/85399 ,  H01L2224/05599

摘要： In a soldering method for Ag-containing lead-free solders to be soldered to an Ag-containing member, void generation is prevented and solder wettability is improved. The soldering method for Ag-containing lead-free solders of the present invention is a soldering method for Ag-containing lead-free solders includes a first step of bringing a lead-free solder having a composition that contains Ag that a relation between a concentration C (mass %) of Ag contained in an Sn—Ag-based lead-free solder before soldering of a mass M(g) and an elution amount B(g) of Ag contained in the Ag-containing member becomes 1.0 mass %≦(M×C+B)×100/(M+B)≦4.6 mass % and that the balance consists of Sn and unavoidable impurities into contact with the Ag-containing member, a second step of heating and melting the lead-free solder, and a third step of cooling the lead-free solder.

摘要翻译： 在将含铂的无铅焊料焊接到含Ag构件的焊接方法中，防止产生空隙并提高焊料润湿性。 本发明的含Ag无铅焊料的焊接方法是含Ag无铅焊料的焊接方法，其包括使具有含Ag组成的无铅焊料成为浓度 含Ag组分中所含的质量M（g）和质量M（g）的Ag和溶出量B（g）之前的Sn-Ag类无铅焊料中所含的Ag的C（质量％）为1.0质量％ （M×C + B）×100 /（M + B）≤4.4质量％，余量由Sn和不可避免的杂质构成与含Ag构件接触，第二步是对无铅焊料进行加热熔融 ，以及冷却无铅焊料的第三步骤。

公开(公告)号：US20170005089A1

公开(公告)日：2017-01-05

申请号：US15265940

申请日：2016-09-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/28 ,  H02M3/155 ,  H01L29/49 ,  H01L29/423 ,  H02M7/00 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在它们之间插入形成区域SDR。

公开(公告)号：US09536854B2

公开(公告)日：2017-01-03

申请号：US14893833

申请日：2015-03-31

申请人： Nippon Micrometal Corporation ,  Nippon Steel & Sumikin Materials Co., Ltd.

发明人： Takashi Yamada ,  Daizo Oda ,  Ryo Oishi ,  Teruo Haibara ,  Tomohiro Uno

IPC分类号： H01B5/00 ,  H01L23/00 ,  B21C1/00 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  B23K35/30 ,  B23K35/02

CPC分类号： H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  B23K35/0227 ,  B23K35/3006 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/45012 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/00015 ,  H01L2924/01201

摘要： Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

摘要翻译： 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 在线中心横截面的方向上，相对于线纵向的角度差为15°以下的晶体方向<100>的面积比为50％〜90％，（3）当 在线表面测定线长方向的晶体方向，晶体方向<100>与线长度方向的角度差为15°以下的面积比为50％〜90％。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。