公开(公告)号：US11842976B2

公开(公告)日：2023-12-12

申请号：US17974391

申请日：2022-10-26

申请人： SJ Semiconductor (Jiangyin) Corporation

发明人： Hanlung Tsai ,  Chengchung Lin ,  Mingchih Chen

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L24/43 ,  H01L21/56 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L23/29 ,  H01L23/296 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/4501 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2224/48464 ,  H01L2224/49051

摘要： The present disclosure provides a chip package structure having a heat sink and a method making the same. The method includes: bonding a chip to a top surface of a package substrate and forming a heat-conducting lead having an arc-shape and placed on the chip in a vertical direction, a first end of the heat-conducting lead is connected with a surface of the chip, and a second end is connected with a solder ball; forming a plastic package material layer that protects the chip and the heat-conducting lead; forming a heat-conducting adhesive layer on the surface of the plastic package material layer, where the heat-conducting adhesive layer is connected with the solder ball on the second end of the heat-conducting lead; and forming a heat dissipation layer on a surface of the heat-conducting adhesive layer. With the present disclosure, the heat dissipation efficiency of the chip is effectively improved.

公开(公告)号：US09859257B2

公开(公告)日：2018-01-02

申请号：US15358380

申请日：2016-11-22

申请人： Invensas Corporation

发明人： Javier A. Delacruz ,  Belgacem Haba ,  Tu Tam Vu ,  Rajesh Katkar

IPC分类号： H01L23/495 ,  H01L21/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49051 ,  H01L2224/4909 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/06 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

公开(公告)号：US20170373055A1

公开(公告)日：2017-12-28

申请号：US15700679

申请日：2017-09-11

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki SHIRAISHI ,  Tomoaki UNO ,  Nobuyoshi MATSUURA

IPC分类号： H01L27/06 ,  H02M3/155 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/8234 ,  H01L21/28 ,  H02M7/00 ,  H01L29/417 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US09793265B2

公开(公告)日：2017-10-17

申请号：US15265940

申请日：2016-09-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L27/06 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L29/78 ,  H02M7/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H02M3/155 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

公开(公告)号：US20170133344A1

公开(公告)日：2017-05-11

申请号：US15253747

申请日：2016-08-31

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Satoru TAKAKU

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/66

CPC分类号： H01L24/49 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/58 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/06179 ,  H01L2224/06517 ,  H01L2224/09179 ,  H01L2224/09517 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49051 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a semiconductor chip having a first surface bonded to the substrate and a second surface that is opposite to the first surface and includes a first electrode pad and a second electrode pad thereon, the first electrode pad being electrically connected to a circuit of the semiconductor chip that is operated during operation of the semiconductor device and the second electrode pad being electrically separated from the circuit, a first wire extending between the first electrode pad and a terminal of the substrate that is electrically connected with an external device during operation of the semiconductor device, a second wire extending between the second electrode pad and the substrate, and a resin layer formed over the second surface of the semiconductor chip and covering the first and second wires.

公开(公告)号：US09613938B2

公开(公告)日：2017-04-04

申请号：US14987892

申请日：2016-01-05

申请人： Soichiro Suzu ,  Tomohito Taki

发明人： Soichiro Suzu ,  Tomohito Taki

IPC分类号： H05K1/18 ,  H01L25/10 ,  H01L23/043 ,  H01L21/54 ,  H01L23/00 ,  H01L25/00 ,  H01L23/16

CPC分类号： H01L25/10 ,  H01L21/54 ,  H01L23/043 ,  H01L23/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/29191 ,  H01L2224/3013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48135 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49051 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85186 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A module includes a first substrate including first electrodes; a first element bonded to the first substrate, and including second electrodes disposed at a first end of the first element and third electrodes disposed at a second end of the first element opposite from the first end; a second substrate stacked on the first substrate and including a recess; and a second element bonded to a bottom surface of the recess of the second substrate and including fourth electrodes. The first electrodes of the first substrate are electrically connected to the second electrodes at the first end of the first element, and the third electrodes at the second end of the first element are electrically connected to the fourth electrodes of the second element via a through hole formed in the bottom surface of the recess.

公开(公告)号：US20160307867A1

公开(公告)日：2016-10-20

申请号：US14831324

申请日：2015-08-20

申请人： SK hynix Inc.

发明人： Jung Tae JEONG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/10

CPC分类号： H01L24/49 ,  H01L23/10 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/562 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48092 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.

摘要翻译： 半导体封装可以包括主衬底，通过间隙与主衬底间隔开的子衬底以及设置在主衬底上的半导体芯片。 半导体封装可以包括配置成将半导体芯片连接到子基板并且包括多个绞合线的绞合线的互连构件。 半导体封装可以包括覆盖主衬底和半导体芯片的主要模制构件和覆盖副衬底的次模制构件。 半导体封装可以包括应力缓冲层，其被配置为填充主衬底和子衬底之间的间隙并且围绕互连构件。

公开(公告)号：US20150380344A1

公开(公告)日：2015-12-31

申请号：US14844427

申请日：2015-09-03

申请人： Semiconductor Components Industries, LLC

发明人： Takeshi Susaki ,  Masahito Shindo ,  Kazumi Onda

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49541 ,  B23K20/005 ,  B23K20/106 ,  B23K2101/42 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00012

摘要： The invention is directed to firm bonding between semiconductor dies etc bonded to a lead frame and wire-bonding portions of the lead frame by ultrasonic Al wire bonding, and the prevention of shortcircuit between the semiconductor dies etc due to a remaining portion of the outer frame of the lead frame after the outer frame is cut. By extending the wire-bonding portion etc on the lead frame in a wire-bonding direction and connecting the wire-bonding portion etc to the outer frame of the lead frame through a connection lead etc, the ultrasonic vibration force in the ultrasonic Al wire bonding is prevented from dispersing and the Al wire and the wire-bonding portion etc are firmly bonded. The outer frame is cut after a resin sealing process is completed. Even when a portion of the outer frame remains on the side surface of the resin package, connection between the connection lead etc and other hanging lead etc are prevented by providing a notch etc in the outer frame between the connection lead etc and the hanging lead etc.

摘要翻译： 本发明涉及通过超声波铝线接合将结合到引线框架和引线框架的引线接合部分的半导体管芯等之间的牢固结合，以及由于外部框架的剩余部分而防止半导体管芯之间的短路 在外框被切割之后的引线框架。 通过在引线框架上引线接合方向延伸引线接合部等，并通过连接引线等将导线接合部等连接到引线框架的外框架上，超声波Al引线接合中的超声波振动力 防止分散，并且Al线和引线接合部等牢固地结合。 在树脂密封过程完成后，外框被切割。 即使当外框的一部分保留在树脂封装的侧表面上时，通过在连接引线等与悬挂引线等之间的外框架中设置切口等来防止连接引线等与其它悬挂引线之间的连接 。

公开(公告)号：US09153686B2

公开(公告)日：2015-10-06

申请号：US14340198

申请日：2014-07-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Masaki Shiraishi ,  Tomoaki Uno ,  Nobuyoshi Matsuura

IPC分类号： H01L23/34 ,  H01L29/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H02M7/00 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L21/28035 ,  H01L21/823475 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48624 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M3/155 ,  H02M7/003

摘要： In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

摘要翻译： 在具有功率MOS·FET高侧开关和功率MOS·FET低侧开关串联的电路的非绝缘DC-DC转换器中，功率MOS·FET低侧开关和肖特基 与功率MOS·FET低侧开关并联连接的二极管形成在一个半导体芯片内。 肖特基势垒二极管的形成区域SDR设置在半导体芯片的较短方向的中央，并且在其两侧设置功率MOS·FET低侧开关的形成区域。 从半导体芯片的主表面的两长边附近的栅极指向肖特基势垒二极管的形成区域SDR，设置多个栅极指，以便在其间插入形成区域SDR。

公开(公告)号：US08703544B2

公开(公告)日：2014-04-22

申请号：US13406919

申请日：2012-02-28

申请人： Wu Hu Li ,  Heng Wan Hong

发明人： Wu Hu Li ,  Heng Wan Hong

IPC分类号： H01L21/50

CPC分类号： H01L23/49582 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48764 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49505 ,  H01L2224/85207 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/20755 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic component and method of making an electronic component is disclosed. In one embodiment, the electronic component includes a frame having a base layer, a first layer, a second layer including palladium placed on the first layer, and a third layer including gold placed on the second layer. A semiconductor chip is positioned on the frame.

摘要翻译： 公开了一种制造电子部件的电子部件和方法。 在一个实施例中，电子部件包括具有基底层，第一层，包括放置在第一层上的钯的第二层以及包含置于第二层上的金的第三层的框架。 半导体芯片位于框架上。