公开(公告)号：US20170148774A1

公开(公告)日：2017-05-25

申请号：US15424080

申请日：2017-02-03

申请人： SK hynix Inc.

发明人： Jung Tae JEONG

IPC分类号： H01L25/10 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.

公开(公告)号：US20170162515A1

公开(公告)日：2017-06-08

申请号：US15079337

申请日：2016-03-24

申请人： SK hynix Inc.

发明人： Seung Ho KIM ,  Soo Won KANG ,  Jung Tae JEONG

IPC分类号： H01L23/552 ,  H01L23/58 ,  H01L25/065 ,  H01L29/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor package and the semiconductor package are provided. The method for manufacturing a semiconductor package may include arranging a conductive elastic plate over a package substrate including through slits disposed along edges of a chip mounting region and a conductive guard rails providing a concave trench shape, and bending the conductive elastic plate. Edge portions of the conductive elastic plate may be inserted into the trenches of the conductive guard rails and supported by the conductive guard rails by a force trying to stretch by the elastic restoring force of the wing portions of the conductive elastic plate.

公开(公告)号：US20160225743A1

公开(公告)日：2016-08-04

申请号：US14729611

申请日：2015-06-03

申请人： SK hynix Inc.

发明人： Jung Tae JEONG

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00

摘要： A bottom package having a first semiconductor chip and first connection members; and a top package disposed over the bottom package, and having a second semiconductor chip and second connection members electrically coupled with the first connection members. The bottom package includes an interposer having electrodes arranged along edges; first bond fingers arranged by being separated from the edges of the interposer; a first semiconductor chip disposed over the interposer to expose the electrodes, and having first bonding pads; first bonding wires electrically coupling the first bonding pads and the electrodes; second bonding wires electrically coupling the electrodes and the first bond fingers; and a first encapsulation member formed to cover the first bond fingers, the upper and side surfaces of the interposer and the first semiconductor chip, and the first and second bonding wires, and having via holes which expose portions of the second bonding wires.

摘要翻译： 一种具有第一半导体芯片和第一连接构件的底部封装; 以及顶部封装，其设置在所述底部封装上方，并且具有与所述第一连接构件电耦合的第二半导体芯片和第二连接构件。 底部封装包括具有沿边缘布置的电极的插入器; 通过从中介层的边缘分离而布置的第一粘合指状物; 设置在所述插入件上方以暴露所述电极并具有第一接合焊盘的第一半导体芯片; 第一接合线，电耦合第一接合焊盘和电极; 第二接合线，电耦合电极和第一接合指; 以及第一密封构件，其形成为覆盖所述第一接合指状物，所述插入件和所述第一半导体芯片的上表面和所述侧表面以及所述第一和第二接合线，并且具有露出所述第二接合线的部分的通孔。

公开(公告)号：US20160295698A1

公开(公告)日：2016-10-06

申请号：US14813359

申请日：2015-07-30

申请人： SK hynix Inc.

发明人： Jung Tae JEONG

IPC分类号： H05K1/18 ,  H05K1/09 ,  H05K1/14 ,  H05K1/11

CPC分类号： H05K1/181 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K3/3436 ,  H05K2201/10287 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.

摘要翻译： 半导体封装模块可以包括第一衬底和布置成面对第一衬底的第二衬底。 半导体封装模块可以包括将第一衬底电连接到第二衬底并且包括多个电线的互连构件。 多个线的一部分可以被扭绞并缠绕在一起，并且可以被弯曲以沿预定方向延伸。

公开(公告)号：US20160079210A1

公开(公告)日：2016-03-17

申请号：US14952191

申请日：2015-11-25

申请人： SK hynix Inc.

发明人： Jung Tae JEONG ,  Il Hwan CHO

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/5386 ,  H01L23/64 ,  H01L24/01 ,  H01L24/05 ,  H01L24/72 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/06187 ,  H01L2224/16198 ,  H01L2224/32225 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.

摘要翻译： 半导体封装包括衬底和堆叠在衬底上的多个半导体芯片。 每个半导体芯片具有前表面，与前表面相对的后表面，连接前表面和后表面的侧壁表面，以预定深度从前表面向后表面延伸的垂直通孔，以及 从侧壁表面横向延伸以连接到垂直通过电极的水平通过电极。 至少一个连接构件设置在半导体芯片的侧壁表面上，以将半导体芯片的水平通过电极彼此连接。 还提供了相关方法。

公开(公告)号：US20160307867A1

公开(公告)日：2016-10-20

申请号：US14831324

申请日：2015-08-20

申请人： SK hynix Inc.

发明人： Jung Tae JEONG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/10

CPC分类号： H01L24/49 ,  H01L23/10 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/562 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/46 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48092 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor package may include a main substrate, a sub-substrate spaced apart from the main substrate by a gap, and a semiconductor chip disposed on the main substrate. The semiconductor package may include an interconnection member configured to connect the semiconductor chip to the sub-substrate and including twisted wires of a plurality of strands. The semiconductor package may include a main molding member covering the main substrate and the semiconductor chip, and a sub-molding member covering the sub-substrate. The semiconductor package may include a stress buffer layer configured to fill the gap between the main substrate and the sub-substrate, and surround the interconnection member.

摘要翻译： 半导体封装可以包括主衬底，通过间隙与主衬底间隔开的子衬底以及设置在主衬底上的半导体芯片。 半导体封装可以包括配置成将半导体芯片连接到子基板并且包括多个绞合线的绞合线的互连构件。 半导体封装可以包括覆盖主衬底和半导体芯片的主要模制构件和覆盖副衬底的次模制构件。 半导体封装可以包括应力缓冲层，其被配置为填充主衬底和子衬底之间的间隙并且围绕互连构件。

公开(公告)号：US20150348930A1

公开(公告)日：2015-12-03

申请号：US14516223

申请日：2014-10-16

申请人： SK hynix Inc.

发明人： Jung Tae JEONG ,  Si Eon KIM ,  Jong Woo AHN

IPC分类号： H01L23/00

CPC分类号： H01L24/17 ,  H01L23/043 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/81191 ,  H01L2924/171 ,  H01L2924/00012 ,  H01L2924/014

摘要： A flip chip package includes a chip having a surface, main bumps disposed on a first region of the surface of the chip, dummy bumps disposed on a second region of the surface of the chip, a substrate having a surface, dams disposed on the surface of the substrate, connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps, and adhesion patterns attaching the dummy bumps to respective ones of the dams.

摘要翻译： 倒装芯片封装包括具有表面的芯片，设置在芯片表面的第一区域上的主凸块，设置在芯片表面的第二区域上的虚设凸块，具有表面的基板， 的衬底，设置在衬底的表面上并连接到相应的主凸起的连接焊盘，以及将虚拟凸块连接到相应的坝。

公开(公告)号：US20150179618A1

公开(公告)日：2015-06-25

申请号：US14254768

申请日：2014-04-16

申请人： SK HYNIX INC.

发明人： Jung Tae JEONG

IPC分类号： H01L25/10 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.

摘要翻译： 提供封装封装（PoP）模块。 PoP模块包括下封装和位于下封装之上的上封装。 下封装包括下基板和设置在下基板的顶表面上的下芯片。 上部封装包括上基板，设置在上基板的顶表面上的多个上芯片，以及设置在多个上芯片上的上成型件。 上模制件被分成至少两个部分，它们通过沟槽彼此分开。 还提供了相关的存储卡和相关的电子系统。